cshrd.h

CS8900 for windows ce 4.2 驱动程序源码

/****************************************************************************
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//---------------------------------------------------------------------------
//
//  Copyright (C) 2002-2003. Unpublished Work of Cirrus Logic Corp.
//  All Rights Reserved.
//
//  THIS WORK IS AN UNPUBLISHED WORK AND CONTAINS CONFIDENTIAL,
//  PROPRIETARY AND TRADE SECRET INFORMATION OF CRYSTAL SEMICONDUCTOR.
//  ACCESS TO THIS WORK IS RESTRICTED TO (I) CRYSTAL SEMICONDUCTOR EMPLOYEES
//  WHO HAVE A NEED TO KNOW TO PERFORM TASKS WITHIN THE SCOPE OF THEIR
//  ASSIGNMENTS  AND (II) ENTITIES OTHER THAN CRYSTAL SEMICONDUCTOR WHO
//  HAVE ENTERED INTO  APPROPRIATE LICENSE AGREEMENTS.  NO PART OF THIS
//  WORK MAY BE USED, PRACTICED, PERFORMED, COPIED, DISTRIBUTED, REVISED,
//  MODIFIED, TRANSLATED, ABRIDGED, CONDENSED, EXPANDED, COLLECTED,
//  COMPILED,LINKED,RECAST, TRANSFORMED, ADAPTED IN ANY FORM OR BY ANY
//  MEANS,MANUAL, MECHANICAL, CHEMICAL, ELECTRICAL, ELECTRONIC, OPTICAL,
//  BIOLOGICAL, OR OTHERWISE WITHOUT THE PRIOR WRITTEN PERMISSION AND
//  CONSENT OF CRYSTAL SEMICONDUCTOR . ANY USE OR EXPLOITATION OF THIS WORK
//  WITHOUT THE PRIOR WRITTEN CONSENT OF CRYSTAL SEMICONDUCTOR  COULD
//  SUBJECT THE PERPETRATOR TO CRIMINAL AND CIVIL LIABILITY.
//
//---------------------------------------------------------------------------

/*++
Copyright (c) 1994  ZeitNet Inc.

Module Name:
    cshrd.h

Abstract:
    This file contains the hardware-related definitions for
    the CRYSTAL driver.


Author:
    Sateesh. A Kumar(Sat).
    Creation date 11-Mar-1994

Environment:
    This driver is expected to work in DOS, OS2 and NT at the equivalent
    of kernel mode.

    Architecturally, there is an assumption in this driver that we are
    on a little endian machine.

Revision History:


12 November 1994 10:00  ASK/PI
  -  Modified PACKET_PAGE structures to reflect changes incorporated
       in data sheet of CS8921 v0.21 October 6 1994.

  -  A new bit CRYSTAL_LCR_NWAY_ENABLE  is introduced in Line control Register.

  -  A new bit CRYSTAL_LCR_NWAY_PULSES  is introduced in Line control Register.

  -  A new bit CRYSTAL_LSR_NWAY_FDX     is introduced in Line Status Register.

  -  A new bit CRYSTAL_LSR_NWAY_ACTIVE is introduced in Line Status Register.

   By                Date
  Prashanth (PI)     5-1-95

Struture for CRYSTAL_DMA_FRAME        is defined

   By      : Prashanth
   DATE    : 19 th May 1995
   VERSION : 0.02

 This code is merged for sparrow and rattler. The Code can auto
 Detect type of card and configure accordingly

   DATE    : 25 th May 1995

     - This header file has defines for  EEPROM Ver .01

   DATE    : 14 th Jun 1995
   VERSION : 1.0

 -----------------------------------------------------------------------------

   DATE    : 10th May 1996
   VERSION : 2.29
   PERSON  : Mike Gibson

   Change Flag:  @250


   Add definition for EEPROM bit that indicates the driver should load
   even if the cable is not attached.
 -----------------------------------------------------------------------------

   DATE    : 07th Nov 1996
   VERSION : 2.30
   PERSON  : Bob Sharp

   Change Flag:  @253

   Added support for detecting Chip Revision
 -----------------------------------------------------------------------------
--*/

#ifndef _CRYSTALHARDWARE_
#define _CRYSTALHARDWARE_

#if ( defined(ARM_PROCESSOR) || defined(SH3_PROCESSOR))
/*The CS8900 has four interrupt request output pins that can be connected
 directly to Processor. Only one interrupt output pin is connected to ARM or SH3.
 CS8900_INTERRUPT_PIN_NUM defines which interrupt pin is used.
 0:  INTRQ0
 1:  INTRQ1
 2:  INTRQ2
 3:  INTRQ3
*/
#define CS8900_INTERRUPT_REQUEST_PIN_NUM     0

/*For SH3: CS8900_IOPORT_MEM_ADDR is the physical memory address of CS8900 IO port.
  For ARM and Strong ARM:  CS8900_IOPORT_MEM_ADDR is the un-buffered & un-cashed 
  virtual address (range 0xA0000000-0xBFFFFFFF).  Its buffered & cashed virtual address
  (ragne 0x80000000-0x9FFFFFFF) should be defined in OEMAddressTable.
   Note: Must be defined according to the target board.*/
#define CS8900_IOPORT_MEM_ADDR     0xC0000000L

#define CRYSTAL_STARTING_PORT   CS8900_IOPORT_MEM_ADDR
#define CRYSTAL_MAX_PORT_ADDRESS   CS8900_IOPORT_MEM_ADDR+1

#else
#define CRYSTAL_STARTING_PORT            0x200
#define CRYSTAL_MAX_PORT_ADDRESS         0x370
#endif
#define CRYSTAL_NEXT_PORT_OFFSET         0x10

//
//  Crystal Port addresses for I/O Space Model.
//
#define  CRYSTAL_RECEIVE_FRAME_PORT             ((USHORT)(0x0000))
#define  CRYSTAL_TRANSMIT_FRAME_PORT            ((USHORT)(0x0000))
#define  CRYSTAL_TRANSMIT_COMMAND_PORT          ((USHORT)(0x0004))
#define  CRYSTAL_TRANSMIT_LENGTH_PORT           ((USHORT)(0x0006))
#define  CRYSTAL_ISQ_PORT                       ((USHORT)(0x0008))
#define  CRYSTAL_ADDRESS_PORT                   ((USHORT)(0x000A))
#define  CRYSTAL_DATA_PORT                      ((USHORT)(0x000C))

#define  CRYSTAL_IO_SIZE                        ((USHORT)(0x0010))   // 16
#define  CRYSTAL_MEMORY_SIZE                    ((USHORT)(0x1000))   // 4K
#define  CRYSTAL_ROM_SIZE                       ((USHORT)(0x4000))   // 16K



//#define CS8921                       0

#define  CS89XX_ID                     0x630e
#define  CS8900_PROD_ID_LOW            0x0
//@105 add mongoose support
#define  CS89xx_PROD_ID_LOW            0x6000  //@105
#define  PRODUCT_ID_MASK               0xE000
#define  REVISION_ID_MASK              0x1f00  //@253
//
// Include processor-specific definitions needed by the CS8921.
// Macros for CRYSTAL_READ_PORT, CRYSTAL_WRITE_PORT etc.

//#include <csdet.h>

#define  CRYSTAL_CHIPEISA_ID                   ((USHORT)(0x0000))    // offset 0-> Corp -ID
#define  CRYSTAL_PRODUCT_ID                    ((USHORT)(0x0002))    // offset 02h
#define  CRYSTAL_ISA_IO_BASE_ADDRESS           ((USHORT)(0x0020))    // offset 20h
#define  CRYSTAL_ISA_INTERRUPT_NUMBER          ((USHORT)(0x0022))    // offset 22h
#define  CRYSTAL_ISA_DMA_CHANNEL               ((USHORT)(0x0024))    // offset 24h
#define  CRYSTAL_ISA_DMA_START_OF_FRAME_OFFSET ((USHORT)(0x0026))    // offset 26h
#define  CRYSTAL_ISA_DMA_FRAME_COUNT           ((USHORT)(0x0028))    // offset 28h
#define  CRYSTAL_ISA_DMA_BYTE_COUNT            ((USHORT)(0x002A))    // offset 2Ah
#define  CRYSTAL_ISA_MEMORY_BASE_ADDRESS       ((USHORT)(0x002C))    // offset 2Ch
#define  CRYSTAL_BOOT_PROM_BASE_ADDRESS        ((USHORT)(0x0030))    // offset 30h
#define  CRYSTAL_BOOT_PROM_ADDRESS_MASK        ((USHORT)(0x0034))    // offset 34h
#define  CRYSTAL_EEPROM_COMMAND_REGISTER       ((USHORT)(0x0040))    // offset 40h
#define  CRYSTAL_EEPROM_DATA_WORD              ((USHORT)(0x0042))    // offset 42h
#define  CRYSTAL_FRAME_BYTE_COUNT              ((USHORT)(0x0050))    // offset 50h  // @258a
#define  CRYSTAL_RX_CONFIG_REGISTER            ((USHORT)(0x0102))    // offset 102h
#define  CRYSTAL_RX_CONTROL_REGISTER           ((USHORT)(0x0104))    // offset 104h
#define  CRYSTAL_TX_CONFIG_REGISTER            ((USHORT)(0x0106))    // offset 106h
#define  CRYSTAL_TX_COMMAND_REGISTER           ((USHORT)(0x0108))    // offset 108h
#define  CRYSTAL_BUFFER_CONFIG_REGISTER        ((USHORT)(0x010A))    // offset 10Ah
#define  CRYSTAL_LINE_CONTROL_REGISTER         ((USHORT)(0x0112))    // offset 112h
#define  CRYSTAL_SELF_CONTROL_REGISTER         ((USHORT)(0x0114))    // offset 114h
#define  CRYSTAL_BUS_CONTROL_REGISTER          ((USHORT)(0x0116))    // offset 116h
#define  CRYSTAL_TEST_CONTROL_REGISTER         ((USHORT)(0x0118))    // offset 118h
#define  CRYSTAL_AUTO_NEG_CONTROL_REGISTER     ((USHORT)(0x011C))     // offset 11Ch
#define  CRYSTAL_INTERRUPT_STATUS_QUEUE        ((USHORT)(0x0120))    // offset 120h
#define  CRYSTAL_RX_EVENT_REGISTER             ((USHORT)(0x0124))    // offset 124h
#define  CRYSTAL_TX_EVENT_REGISTER             ((USHORT)(0x0128))    // offset 128h
#define  CRYSTAL_BUF_EVENT_REGISTER            ((USHORT)(0x012C))    // offset 12Ch
#define  CRYSTAL_RX_MISS_COUNT                 ((USHORT)(0x0130))    // offset 130h
#define  CRYSTAL_TX_COL_COUNT                  ((USHORT)(0x0132))    // offset 132h
#define  CRYSTAL_LINE_STATUS_REGISTER          ((USHORT)(0x0134))    // offset 134h
#define  CRYSTAL_SELF_STATUS_REGISTER          ((USHORT)(0x0136))    // offset 136h
#define  CRYSTAL_BUS_STATUS_REGISTER           ((USHORT)(0x0138))    // offset 138h
#define  CRYSTAL_TDR_REGISTER                  ((USHORT)(0x013C))    // offset 13Ch
#define  CRYSTAL_AUTO_NEG_STATUS_REGISTER      ((USHORT)(0x013E))    // offset 13Eh
#define  CRYSTAL_TX_COMMAND                    ((USHORT)(0x0144))    // offset 144h
#define  CRYSTAL_TX_LENGTH                     ((USHORT)(0x0146))    // offset 146h
#define  CRYSTAL_LOGICAL_ADDRESS_FILTER        ((USHORT)(0x0150))    // offset 150h
#define  CRYSTAL_INDIVIDUAL_ADDRESS            ((USHORT)(0x0158))    // offset 158h
#define  CRYSTAL_RECEIVE_STATUS                ((USHORT)(0x0400))    // offset 400h
#define  CRYSTAL_RECEIVE_LENGTH                ((USHORT)(0x0402))    // offset 402h
#define  CRYSTAL_RECEIVE_FRAME_PTR             ((USHORT)(0x0404))    // offset 404h
#define  CRYSTAL_TRANSMIT_FRAME_PTR            ((USHORT)(0x0A00))    // offset A00h





//
//   CRYSTAL ISA PACKET PAGE STRUCTURE FOR MEMORY MAPPED I/O.
//
//