📄 dly0_1s.inc
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;-----------------------------------------------;
;; ;
;#INCLUDE <DLY0_1S.INC> ;
;; ;
;; delay 0.1 sec ;
;; for 16 MHz ;
;===============================================;
;
; define RAM
;
CBLOCK
R0_DLY0_1S, R1_DLY0_1S, R2_DLY0_1S
ENDC
;
DLY0_1S:
MOVLW 10 ; 10*10mS=0.1S
MOVWF R2_DLY0_1S
DLY0_1S3:
MOVLW 100 ; 100*0.1mS=10mS
MOVWF R1_DLY0_1S
DLY0_1S2:
MOVLW 100 ; 100*1uS=0.1mS
MOVWF R0_DLY0_1S
DLY0_1S1:
NOP ; 1ck
DECFSZ R0_DLY0_1S ; 1ck
GOTO DLY0_1S1 ; 2ck(totaly 4 ck=1uS)
;
DECFSZ R1_DLY0_1S
GOTO DLY0_1S2
;
DECFSZ R2_DLY0_1S
GOTO DLY0_1S3
RETURN
;
;
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