lpc177x_8x_gpdma.c

LPC1788的USBHOST的FATFS移植

/**********************************************************************
* $Id$		lpc177x_8x_gpdma.c			2011-06-02
*//**
* @file		lpc177x_8x_gpdma.c
* @brief	Contains all functions support for GPDMA firmware library
*			on LPC177x_8x
* @version	1.0
* @date		02. June. 2011
* @author	NXP MCU SW Application Team
* 
* Copyright(C) 2011, NXP Semiconductor
* All rights reserved.
*
***********************************************************************
* Software that is described herein is for illustrative purposes only
* which provides customers with programming information regarding the
* products. This software is supplied "AS IS" without any warranties.
* NXP Semiconductors assumes no responsibility or liability for the
* use of the software, conveys no license or title under any patent,
* copyright, or mask work right to the product. NXP Semiconductors
* reserves the right to make changes in the software without
* notification. NXP Semiconductors also make no representation or
* warranty that such application will be suitable for the specified
* use without further testing or modification.
**********************************************************************/

/* Peripheral group ----------------------------------------------------------- */
/** @addtogroup GPDMA
 * @{
 */

/* Includes ------------------------------------------------------------------- */
#include "lpc177x_8x_gpdma.h"
#include "lpc177x_8x_clkpwr.h"

/* Private Variables ---------------------------------------------------------- */
/** @defgroup GPDMA_Private_Variables GPDMA Private Variables
 * @{
 */

/**
 * @brief Lookup Table of Connection Type matched with
 * Peripheral Data (FIFO) register base address
 */
#ifdef __IAR_SYSTEMS_ICC__
volatile const void *GPDMA_LUTPerAddr[] = {
		0,								// Revered
		(&LPC_MCI->FIFO),				// SD Card
		(&LPC_SSP0->DR),				// SSP0 Tx
		(&LPC_SSP0->DR),				// SSP0 Rx
		(&LPC_SSP1->DR),				// SSP1 Tx
		(&LPC_SSP1->DR),				// SSP1 Rx
		(&LPC_SSP2->DR),				// SSP2 Tx
		(&LPC_SSP2->DR),				// SSP2 Rx
		(&LPC_ADC->GDR),				// ADC
		(&LPC_DAC->CR),					// DAC
		(&LPC_UART0->/*RBTHDLR.*/THR),	// UART0 Tx
		(&LPC_UART0->/*RBTHDLR.*/RBR),	// UART0 Rx
		(&LPC_UART1->/*RBTHDLR.*/THR),	// UART1 Tx
		(&LPC_UART1->/*RBTHDLR.*/RBR),	// UART1 Rx
		(&LPC_UART2->/*RBTHDLR.*/THR),	// UART2 Tx
		(&LPC_UART2->/*RBTHDLR.*/RBR),	// UART2 Rx
		(&LPC_TIM0->MR0),				// MAT0.0
		(&LPC_TIM0->MR1),				// MAT0.1
		(&LPC_TIM1->MR0),				// MAT1.0
		(&LPC_TIM1->MR1),				// MAT1.1
		(&LPC_TIM2->MR0),				// MAT2.0
		(&LPC_TIM2->MR1),				// MAT2.1
		(&LPC_I2S->TXFIFO), 			// I2S Tx
		(&LPC_I2S->RXFIFO), 			// I2S Rx
		0,								// Reverse
		0,								// Reverse
		(&LPC_UART3->/*RBTHDLR.*/THR),	// UART3 Tx
		(&LPC_UART3->/*RBTHDLR.*/RBR),	// UART3 Rx
		(&LPC_UART4->/*RBTHDLR.*/THR),	// UART4 Tx
		(&LPC_UART4->/*RBTHDLR.*/RBR),	// UART4 Rx
		(&LPC_TIM3->MR0),				// MAT3.0
		(&LPC_TIM3->MR1),				// MAT3.1
};
#else
const uint32_t GPDMA_LUTPerAddr[] = {
		0, 											// Reversed
		((uint32_t)&LPC_MCI->FIFO),					// SD Card
		((uint32_t)&LPC_SSP0->DR),					// SSP0 Tx
		((uint32_t)&LPC_SSP0->DR),					// SSP0 Rx
		((uint32_t)&LPC_SSP1->DR),					// SSP1 Tx
		((uint32_t)&LPC_SSP1->DR),					// SSP1 Rx
		((uint32_t)&LPC_SSP2->DR),					// SSP2 Tx
		((uint32_t)&LPC_SSP2->DR),					// SSP2 Rx
		((uint32_t)&LPC_ADC->GDR),					// ADC
		((uint32_t)&LPC_DAC->CR),					// DAC
		((uint32_t)&LPC_UART0->/*RBTHDLR.*/THR),	// UART0 Tx
		((uint32_t)&LPC_UART0->/*RBTHDLR.*/RBR),	// UART0 Rx
		((uint32_t)&LPC_UART1->/*RBTHDLR.*/THR),	// UART1 Tx
		((uint32_t)&LPC_UART1->/*RBTHDLR.*/RBR),	// UART1 Rx
		((uint32_t)&LPC_UART2->/*RBTHDLR.*/THR),	// UART2 Tx
		((uint32_t)&LPC_UART2->/*RBTHDLR.*/RBR),	// UART2 Rx
		((uint32_t)&LPC_TIM0->MR0),					// MAT0.0
		((uint32_t)&LPC_TIM0->MR1),					// MAT0.1
		((uint32_t)&LPC_TIM1->MR0),					// MAT1.0
		((uint32_t)&LPC_TIM1->MR1),					// MAT1.1
		((uint32_t)&LPC_TIM2->MR0),					// MAT2.0
		((uint32_t)&LPC_TIM2->MR1),					// MAT2.1
		((uint32_t)&LPC_I2S->TXFIFO), 				// I2S Tx
		((uint32_t)&LPC_I2S->RXFIFO), 				// I2S Rx
		0,											// Reverse
		0,											// Reverse
		((uint32_t)&LPC_UART3->/*RBTHDLR.*/THR),	// UART3 Tx
		((uint32_t)&LPC_UART3->/*RBTHDLR.*/RBR),	// UART3 Rx
		((uint32_t)&LPC_UART4->/*RBTHDLR.*/THR),	// UART4 Tx
		((uint32_t)&LPC_UART4->/*RBTHDLR.*/RBR),	// UART4 Rx
		((uint32_t)&LPC_TIM3->MR0),					// MAT3.0
		((uint32_t)&LPC_TIM3->MR1),					// MAT3.1
};
#endif
/**
 * @brief Lookup Table of GPDMA Channel Number matched with
 * GPDMA channel pointer
 */
const LPC_GPDMACH_TypeDef *pGPDMACh[8] = {
		LPC_GPDMACH0,	// GPDMA Channel 0
		LPC_GPDMACH1,	// GPDMA Channel 1
		LPC_GPDMACH2,	// GPDMA Channel 2
		LPC_GPDMACH3,	// GPDMA Channel 3
		LPC_GPDMACH4,	// GPDMA Channel 4
		LPC_GPDMACH5,	// GPDMA Channel 5
		LPC_GPDMACH6,	// GPDMA Channel 6
		LPC_GPDMACH7,	// GPDMA Channel 7
};
/**
 * @brief Optimized Peripheral Source and Destination burst size
 */
const uint8_t GPDMA_LUTPerBurst[] = {
		0,							// Reserved
		GPDMA_BSIZE_32,				// SD Card
		GPDMA_BSIZE_4,				// SSP0 Tx
		GPDMA_BSIZE_4,				// SSP0 Rx
		GPDMA_BSIZE_4,				// SSP1 Tx
		GPDMA_BSIZE_4,				// SSP1 Rx
		GPDMA_BSIZE_4,				// SSP2 Tx
		GPDMA_BSIZE_4,				// SSP2 Rx
		GPDMA_BSIZE_4,				// ADC
		GPDMA_BSIZE_1,				// DAC
		GPDMA_BSIZE_1,				// UART0 Tx
		GPDMA_BSIZE_1,				// UART0 Rx
		GPDMA_BSIZE_1,				// UART1 Tx
		GPDMA_BSIZE_1,				// UART1 Rx
		GPDMA_BSIZE_1,				// UART2 Tx
		GPDMA_BSIZE_1,				// UART2 Rx
		GPDMA_BSIZE_1,				// MAT0.0
		GPDMA_BSIZE_1,				// MAT0.1
		GPDMA_BSIZE_1,				// MAT1.0
		GPDMA_BSIZE_1,				// MAT1.1
		GPDMA_BSIZE_1,				// MAT2.0
		GPDMA_BSIZE_1,				// MAT2.1
		GPDMA_BSIZE_32, 			// I2S channel 0
		GPDMA_BSIZE_32, 			// I2S channel 1
		0,							// Reserved
		0, 							// Reserved
		GPDMA_BSIZE_1,				// UART3 Tx
		GPDMA_BSIZE_1,				// UART3 Rx
		GPDMA_BSIZE_1,				// UART4 Tx
		GPDMA_BSIZE_1,				// UART4 Rx
		GPDMA_BSIZE_1,				// MAT3.0
		GPDMA_BSIZE_1,				// MAT3.1
};
/**
 * @brief Optimized Peripheral Source and Destination transfer width
 */
const uint8_t GPDMA_LUTPerWid[] = {
		0,								// Reserved
		GPDMA_WIDTH_WORD,				// SD Card
		GPDMA_WIDTH_BYTE,				// SSP0 Tx
		GPDMA_WIDTH_BYTE,				// SSP0 Rx
		GPDMA_WIDTH_BYTE,				// SSP1 Tx
		GPDMA_WIDTH_HALFWORD,				// SSP1 Rx
		GPDMA_WIDTH_BYTE,				// SSP2 Tx
		GPDMA_WIDTH_BYTE,				// SSP2 Rx
		GPDMA_WIDTH_WORD,				// ADC
		GPDMA_WIDTH_BYTE,				// DAC
		GPDMA_WIDTH_BYTE,				// UART0 Tx
		GPDMA_WIDTH_BYTE,				// UART0 Rx
		GPDMA_WIDTH_BYTE,				// UART1 Tx
		GPDMA_WIDTH_BYTE,				// UART1 Rx
		GPDMA_WIDTH_BYTE,				// UART2 Tx
		GPDMA_WIDTH_BYTE,				// UART2 Rx
		GPDMA_WIDTH_WORD,				// MAT0.0
		GPDMA_WIDTH_WORD,				// MAT0.1
		GPDMA_WIDTH_WORD,				// MAT1.0
		GPDMA_WIDTH_WORD,				// MAT1.1
		GPDMA_WIDTH_WORD,				// MAT2.0
		GPDMA_WIDTH_WORD,				// MAT2.1
		GPDMA_WIDTH_WORD, 				// I2S channel 0
		GPDMA_WIDTH_WORD, 				// I2S channel 1
		0,								// Reserved
		0, 								// Reserved
		GPDMA_WIDTH_BYTE,				// UART3 Tx
		GPDMA_WIDTH_BYTE,				// UART3 Rx
		GPDMA_WIDTH_BYTE,				// UART4 Tx
		GPDMA_WIDTH_BYTE,				// UART4 Rx
		GPDMA_WIDTH_WORD,				// MAT3.0
		GPDMA_WIDTH_WORD,				// MAT3.1
};

/**
 * @}
 */

/* Public Functions ----------------------------------------------------------- */
/** @addtogroup GPDMA_Public_Functions
 * @{
 */

/********************************************************************//**
 * @brief 		Initialize GPDMA controller
 * @param 		None
 * @return 		None
 *********************************************************************/
void GPDMA_Init(void)
{
	/* Enable GPDMA clock */
	CLKPWR_ConfigPPWR (CLKPWR_PCONP_PCGPDMA, ENABLE);

	// Reset all channel configuration register
	LPC_GPDMACH0->CConfig = 0;
	LPC_GPDMACH1->CConfig = 0;
	LPC_GPDMACH2->CConfig = 0;
	LPC_GPDMACH3->CConfig = 0;
	LPC_GPDMACH4->CConfig = 0;
	LPC_GPDMACH5->CConfig = 0;
	LPC_GPDMACH6->CConfig = 0;
	LPC_GPDMACH7->CConfig = 0;

	/* Clear all DMA interrupt and error flag */
	LPC_GPDMA->IntTCClear = 0xFF;
	LPC_GPDMA->IntErrClr = 0xFF;
}