lpc177x_8x_qei.h

LPC1788的USBHOST的FATFS移植

/** Clear Bit Indicates that the index compare value is equal to the current index count */
#define QEI_INTCLR_REV_Int			((uint32_t)(1<<9))
/** Clear Bit that combined position 0 and revolution count interrupt */
#define QEI_INTCLR_POS0REV_Int		((uint32_t)(1<<10))
/** Clear Bit that Combined position 1 and revolution count interrupt */
#define QEI_INTCLR_POS1REV_Int		((uint32_t)(1<<11))
/** Clear Bit that Combined position 2 and revolution count interrupt */
#define QEI_INTCLR_POS2REV_Int		((uint32_t)(1<<12))
/** QEI Interrupt Clear register bit-mask */
#define QEI_INTCLR_BITMASK			((uint32_t)(0xFFFF))

/*********************************************************************//**
 * Macro defines for QEI Interrupt Enable register
 **********************************************************************/
/** Enabled Interrupt Bit Indicates that an index pulse was detected */
#define QEI_INTEN_INX_Int			((uint32_t)(1<<0))
/** Enabled Interrupt Bit Indicates that a velocity timer overflow occurred */
#define QEI_INTEN_TIM_Int			((uint32_t)(1<<1))
/** Enabled Interrupt Bit Indicates that capture velocity is less than compare velocity */
#define QEI_INTEN_VELC_Int			((uint32_t)(1<<2))
/** Enabled Interrupt Bit Indicates that a change of direction was detected */
#define QEI_INTEN_DIR_Int			((uint32_t)(1<<3))
/** Enabled Interrupt Bit Indicates that an encoder phase error was detected */
#define QEI_INTEN_ERR_Int			((uint32_t)(1<<4))
/** Enabled Interrupt Bit Indicates that and encoder clock pulse was detected */
#define QEI_INTEN_ENCLK_Int			((uint32_t)(1<<5))
/** Enabled Interrupt Bit Indicates that the position 0 compare value is equal to the current position */
#define QEI_INTEN_POS0_Int			((uint32_t)(1<<6))
/** Enabled Interrupt Bit Indicates that the position 1compare value is equal to the current position */
#define QEI_INTEN_POS1_Int			((uint32_t)(1<<7))
/** Enabled Interrupt Bit Indicates that the position 2 compare value is equal to the current position */
#define QEI_INTEN_POS2_Int			((uint32_t)(1<<8))
/** Enabled Interrupt Bit Indicates that the index compare value is equal to the current index count */
#define QEI_INTEN_REV_Int			((uint32_t)(1<<9))
/** Enabled Interrupt Bit that combined position 0 and revolution count interrupt */
#define QEI_INTEN_POS0REV_Int		((uint32_t)(1<<10))
/** Enabled Interrupt Bit that Combined position 1 and revolution count interrupt */
#define QEI_INTEN_POS1REV_Int		((uint32_t)(1<<11))
/** Enabled Interrupt Bit that Combined position 2 and revolution count interrupt */
#define QEI_INTEN_POS2REV_Int		((uint32_t)(1<<12))
/** QEI Interrupt Enable register bit-mask */
#define QEI_INTEN_BITMASK			((uint32_t)(0x1FFF))

/*********************************************************************//**
 * Macro defines for QEI Interrupt Enable Set register
 **********************************************************************/
/** Set Enable Interrupt Bit Indicates that an index pulse was detected */
#define QEI_IESET_INX_Int			((uint32_t)(1<<0))
/** Set Enable Interrupt Bit Indicates that a velocity timer overflow occurred */
#define QEI_IESET_TIM_Int			((uint32_t)(1<<1))
/** Set Enable Interrupt Bit Indicates that capture velocity is less than compare velocity */
#define QEI_IESET_VELC_Int			((uint32_t)(1<<2))
/** Set Enable Interrupt Bit Indicates that a change of direction was detected */
#define QEI_IESET_DIR_Int			((uint32_t)(1<<3))
/** Set Enable Interrupt Bit Indicates that an encoder phase error was detected */
#define QEI_IESET_ERR_Int			((uint32_t)(1<<4))
/** Set Enable Interrupt Bit Indicates that and encoder clock pulse was detected */
#define QEI_IESET_ENCLK_Int			((uint32_t)(1<<5))
/** Set Enable Interrupt Bit Indicates that the position 0 compare value is equal to 
* the current position */
#define QEI_IESET_POS0_Int			((uint32_t)(1<<6))
/** Set Enable Interrupt Bit Indicates that the position 1compare value is equal to 
* the current position */
#define QEI_IESET_POS1_Int			((uint32_t)(1<<7))
/** Set Enable Interrupt Bit Indicates that the position 2 compare value is equal to 
* the current position */
#define QEI_IESET_POS2_Int			((uint32_t)(1<<8))
/** Set Enable Interrupt Bit Indicates that the index compare value is equal to the 
* current index count */
#define QEI_IESET_REV_Int			((uint32_t)(1<<9))
/** Set Enable Interrupt Bit that combined position 0 and revolution count interrupt */
#define QEI_IESET_POS0REV_Int		((uint32_t)(1<<10))
/** Set Enable Interrupt Bit that Combined position 1 and revolution count interrupt */
#define QEI_IESET_POS1REV_Int		((uint32_t)(1<<11))
/** Set Enable Interrupt Bit that Combined position 2 and revolution count interrupt */
#define QEI_IESET_POS2REV_Int		((uint32_t)(1<<12))
/** QEI Interrupt Enable Set register bit-mask */
#define QEI_IESET_BITMASK			((uint32_t)(0x1FFF))

/*********************************************************************//**
 * Macro defines for QEI Interrupt Enable Clear register
 **********************************************************************/
/** Clear Enabled Interrupt Bit Indicates that an index pulse was detected */
#define QEI_IECLR_INX_Int			((uint32_t)(1<<0))
/** Clear Enabled Interrupt Bit Indicates that a velocity timer overflow occurred */
#define QEI_IECLR_TIM_Int			((uint32_t)(1<<1))
/** Clear Enabled Interrupt Bit Indicates that capture velocity is less than compare velocity */
#define QEI_IECLR_VELC_Int			((uint32_t)(1<<2))
/** Clear Enabled Interrupt Bit Indicates that a change of direction was detected */
#define QEI_IECLR_DIR_Int			((uint32_t)(1<<3))
/** Clear Enabled Interrupt Bit Indicates that an encoder phase error was detected */
#define QEI_IECLR_ERR_Int			((uint32_t)(1<<4))
/** Clear Enabled Interrupt Bit Indicates that and encoder clock pulse was detected */
#define QEI_IECLR_ENCLK_Int			((uint32_t)(1<<5))
/** Clear Enabled Interrupt Bit Indicates that the position 0 compare value is equal to the
* current position */
#define QEI_IECLR_POS0_Int			((uint32_t)(1<<6))
/** Clear Enabled Interrupt Bit Indicates that the position 1compare value is equal to the
* current position */
#define QEI_IECLR_POS1_Int			((uint32_t)(1<<7))
/** Clear Enabled Interrupt Bit Indicates that the position 2 compare value is equal to the
* current position */
#define QEI_IECLR_POS2_Int			((uint32_t)(1<<8))
/** Clear Enabled Interrupt Bit Indicates that the index compare value is equal to the current
* index count */
#define QEI_IECLR_REV_Int			((uint32_t)(1<<9))
/** Clear Enabled Interrupt Bit that combined position 0 and revolution count interrupt */
#define QEI_IECLR_POS0REV_Int		((uint32_t)(1<<10))
/** Clear Enabled Interrupt Bit that Combined position 1 and revolution count interrupt */
#define QEI_IECLR_POS1REV_Int		((uint32_t)(1<<11))
/** Clear Enabled Interrupt Bit that Combined position 2 and revolution count interrupt */
#define QEI_IECLR_POS2REV_Int		((uint32_t)(1<<12))
/** QEI Interrupt Enable Clear register bit-mask */
#define QEI_IECLR_BITMASK			((uint32_t)(0xFFFF))


/* ---------------- CHECK PARAMETER DEFINITIONS ---------------------------- */
/* Macro check QEI peripheral */
#define PARAM_QEIx(n)	((n==LPC_QEI))

/* Macro check QEI reset type */
#define PARAM_QEI_RESET(n)	((n==QEI_CON_RESP) \
									|| (n==QEI_RESET_POSOnIDX) \
									|| (n==QEI_RESET_VEL) \
									|| (n==QEI_RESET_IDX))

/* Macro check QEI Direction invert mode */
#define PARAM_QEI_DIRINV(n)	((n==QEI_DIRINV_NONE) || (n==QEI_DIRINV_CMPL))

/* Macro check QEI signal mode */
#define PARAM_QEI_SIGNALMODE(n)	((n==QEI_SIGNALMODE_QUAD) || (n==QEI_SIGNALMODE_CLKDIR))

/* Macro check QEI Capture mode */
#define PARAM_QEI_CAPMODE(n)	((n==QEI_CAPMODE_2X) || (n==QEI_CAPMODE_4X))

/* Macro check QEI Invert index mode */
#define PARAM_QEI_INVINX(n)		((n==QEI_INVINX_NONE) || (n==QEI_INVINX_EN))

/* Macro check QEI Direction invert mode */
#define PARAM_QEI_TIMERRELOAD(n)	((n==QEI_TIMERRELOAD_TICKVAL) || (n==QEI_TIMERRELOAD_USVAL))

/* Macro check QEI status type */
#define PARAM_QEI_STATUS(n)		((n==QEI_STATUS_DIR))

/* Macro check QEI combine position type */
#define PARAM_QEI_COMPPOS_CH(n)		((n==QEI_COMPPOS_CH_0) || (n==QEI_COMPPOS_CH_1) || (n==QEI_COMPPOS_CH_2))

/* Macro check QEI interrupt flag type */
#define PARAM_QEI_INTFLAG(n)	((n==QEI_INTFLAG_INX_Int) \
									|| (n==QEI_INTFLAG_TIM_Int) \
									|| (n==QEI_INTFLAG_VELC_Int) \
									|| (n==QEI_INTFLAG_DIR_Int) \
									|| (n==QEI_INTFLAG_ERR_Int) \
									|| (n==QEI_INTFLAG_ENCLK_Int) \
									|| (n==QEI_INTFLAG_POS0_Int) \
									|| (n==QEI_INTFLAG_POS1_Int) \
									|| (n==QEI_INTFLAG_POS2_Int) \
									|| (n==QEI_INTFLAG_REV_Int) \
									|| (n==QEI_INTFLAG_POS0REV_Int) \
									|| (n==QEI_INTFLAG_POS1REV_Int) \
									|| (n==QEI_INTFLAG_POS2REV_Int))
/**
 * @}
 */

/* Public Types --------------------------------------------------------------- */
/** @defgroup QEI_Public_Types QEI Public Types
 * @{
 */

/**
 * @brief QEI Configuration structure type definition
 */
typedef struct 
{
	uint32_t DirectionInvert	:1; 	/**< Direction invert option:
										- QEI_DIRINV_NONE: QEI Direction is normal
										- QEI_DIRINV_CMPL: QEI Direction is complemented
										*/
	uint32_t SignalMode			:1; 	/**< Signal mode Option:
										- QEI_SIGNALMODE_QUAD: Signal is in Quadrature phase mode
										- QEI_SIGNALMODE_CLKDIR: Signal is in Clock/Direction mode
										*/
	uint32_t CaptureMode		:1;		/**< Capture Mode Option:
										- QEI_CAPMODE_2X: Only Phase-A edges are counted (2X)
										- QEI_CAPMODE_4X: BOTH Phase-A and Phase-B edges are counted (4X)
										*/
	uint32_t InvertIndex		:1; 	/**< Invert Index Option:
										- QEI_INVINX_NONE: the sense of the index input is normal
										- QEI_INVINX_EN: inverts the sense of the index input
										*/
} QEI_CFG_Type;

/**
 * @brief Timer Reload Configuration structure type definition
 */
typedef struct 
{

	uint8_t ReloadOption;		/**< Velocity Timer Reload Option, should be:
								- QEI_TIMERRELOAD_TICKVAL: Reload value in absolute value
								- QEI_TIMERRELOAD_USVAL: Reload value in microsecond value
								*/
	uint8_t Reserved[3];
	uint32_t ReloadValue;		/**< Velocity Timer Reload Value, 32-bit long, should be matched
								with Velocity Timer Reload Option
								*/
} QEI_RELOADCFG_Type;

typedef struct
{
	uint32_t PHA_FilterVal;//FILTERPHA register input
	uint32_t PHB_FilterVal;//FILTERPHB register input
	uint32_t INX_FilterVal;//FILTERINX register input
} st_Qei_FilterCfg;


/**
 * @}
 */





/* Public Functions ----------------------------------------------------------- */
/** @defgroup QEI_Public_Functions QEI Public Functions
 * @{
 */

void QEI_Reset(uint8_t qeiId, uint32_t ulResetType);
void QEI_Init(uint8_t qeiId, QEI_CFG_Type *QEI_ConfigStruct);
void QEI_GetCfgDefault(QEI_CFG_Type *QIE_InitStruct);
void QEI_DeInit(uint8_t qeiId);
FlagStatus QEI_GetStatus(uint8_t qeiId, uint32_t ulFlagType);
uint32_t QEI_GetPosition(uint8_t qeiId);
void QEI_SetMaxPosition(uint8_t qeiId, uint32_t ulMaxPos);
void QEI_SetPositionComp(uint8_t qeiId, uint8_t bPosCompCh, uint32_t ulPosComp);
uint32_t QEI_GetIndex(uint8_t qeiId);
void QEI_SetIndexComp(uint8_t qeiId, uint32_t ulIndexComp);
void QEI_SetTimerReload(uint8_t qeiId, QEI_RELOADCFG_Type *QEIReloadStruct);
uint32_t QEI_GetTimer(uint8_t qeiId);
uint32_t QEI_GetVelocity(uint8_t qeiId);
uint32_t QEI_GetVelocityCap(uint8_t qeiId);
void QEI_SetVelocityComp(uint8_t qeiId, uint32_t ulVelComp);
void QEI_SetDigiFilter(uint8_t qeiId, st_Qei_FilterCfg FilterVal);
FlagStatus QEI_GetIntStatus(uint8_t qeiId, uint32_t ulIntType);
void QEI_IntCmd(uint8_t qeiId, uint32_t ulIntType, FunctionalState NewState);
void QEI_IntSet(uint8_t qeiId, uint32_t ulIntType);
void QEI_IntClear(uint8_t qeiId, uint32_t ulIntType);
uint32_t QEI_CalculateRPM(uint8_t qeiId, uint32_t ulVelCapValue, uint32_t ulPPR);


/**
 * @}
 */

#ifdef __cplusplus
}
#endif

#endif /* __LPC17X_8X_QEI_H_ */

/**
 * @}
 */

/* --------------------------------- End Of File ------------------------------ */