lpc177x_8x_gpdma.h

LPC1788的USBHOST的FATFS移植

/**********************************************************************
* $Id$		lpc177x_8x_gpdma.h			2011-06-02
*//**
* @file		lpc177x_8x_gpdma.h
* @brief	Contains all macro definitions and function prototypes
*			support for GPDMA firmware library on LPC177x_8x
* @version	1.0
* @date		02. June. 2011
* @author	NXP MCU SW Application Team
* 
* Copyright(C) 2011, NXP Semiconductor
* All rights reserved.
*
***********************************************************************
* Software that is described herein is for illustrative purposes only
* which provides customers with programming information regarding the
* products. This software is supplied "AS IS" without any warranties.
* NXP Semiconductors assumes no responsibility or liability for the
* use of the software, conveys no license or title under any patent,
* copyright, or mask work right to the product. NXP Semiconductors
* reserves the right to make changes in the software without
* notification. NXP Semiconductors also make no representation or
* warranty that such application will be suitable for the specified
* use without further testing or modification.
**********************************************************************/

/* Peripheral group ----------------------------------------------------------- */
/** @defgroup GPDMA	GPDMA (General Purpose Direct Memory Access)
 * @ingroup LPC177x_8xCMSIS_FwLib_Drivers
 * @{
 */

#ifndef __LPC177X_8X_GPDMA_H_
#define __LPC177X_8X_GPDMA_H_

/* Includes ------------------------------------------------------------------- */
#include "LPC177x_8x.h"
#include "lpc_types.h"


#ifdef __cplusplus
extern "C"
{
#endif

/* Public Macros -------------------------------------------------------------- */
/** @defgroup GPDMA_Public_Macros GPDMA Public Macros
 * @{
 */

/** DMA Connection number definitions */
#define GPDMA_CONN_MCI				((1UL))			/** SD card */
#define GPDMA_CONN_SSP0_Tx 			((2UL)) 		/**< SSP0 Tx */
#define GPDMA_CONN_SSP0_Rx 			((3UL)) 		/**< SSP0 Rx */
#define GPDMA_CONN_SSP1_Tx 			((4UL)) 		/**< SSP1 Tx */
#define GPDMA_CONN_SSP1_Rx 			((5UL)) 		/**< SSP1 Rx */
#define GPDMA_CONN_SSP2_Tx			((6UL))			/**< SSP2 Tx */
#define GPDMA_CONN_SSP2_Rx			((7UL))			/**< SSP2 Rx */
#define GPDMA_CONN_ADC 				((8UL)) 		/**< ADC */
#define GPDMA_CONN_DAC 				((9UL)) 		/**< DAC */
#define GPDMA_CONN_UART0_Tx			((10UL)) 		/**< UART0 Tx */
#define GPDMA_CONN_UART0_Rx			((11UL)) 		/**< UART0 Rx */
#define GPDMA_CONN_UART1_Tx			((12UL)) 		/**< UART1 Tx */
#define GPDMA_CONN_UART1_Rx			((13UL)) 		/**< UART1 Rx */
#define GPDMA_CONN_UART2_Tx			((14UL)) 		/**< UART2 Tx */
#define GPDMA_CONN_UART2_Rx			((15UL)) 		/**< UART2 Rx */
#define GPDMA_CONN_MAT0_0 			((16UL)) 		/**< MAT0.0 */
#define GPDMA_CONN_MAT0_1 			((17UL)) 		/**< MAT0.1 */
#define GPDMA_CONN_MAT1_0 			((18UL)) 		/**< MAT1.0 */
#define GPDMA_CONN_MAT1_1   		((19UL)) 		/**< MAT1.1 */
#define GPDMA_CONN_MAT2_0   		((20UL)) 		/**< MAT2.0 */
#define GPDMA_CONN_MAT2_1   		((21UL)) 		/**< MAT2.1 */
#define GPDMA_CONN_I2S_Channel_0 	((22UL)) 		/**< I2S channel 0 */
#define GPDMA_CONN_I2S_Channel_1 	((23UL)) 		/**< I2S channel 1 */
#define GPDMA_CONN_UART3_Tx			((26UL)) 		/**< UART3 Tx */
#define GPDMA_CONN_UART3_Rx			((27UL)) 		/**< UART3 Rx */
#define GPDMA_CONN_UART4_Tx			((28UL)) 		/**< UART3 Tx */
#define GPDMA_CONN_UART4_Rx			((29UL)) 		/**< UART3 Rx */
#define GPDMA_CONN_MAT3_0 			((30UL)) 		/**< MAT3.0 */
#define GPDMA_CONN_MAT3_1   		((31UL)) 		/**< MAT3.1 */

/** GPDMA Transfer type definitions: Memory to memory - DMA control */
#define GPDMA_TRANSFERTYPE_M2M 		((0UL))
/** GPDMA Transfer type definitions: Memory to peripheral - DMA control */
#define GPDMA_TRANSFERTYPE_M2P 		((1UL))
/** GPDMA Transfer type definitions: Peripheral to memory - DMA control */
#define GPDMA_TRANSFERTYPE_P2M 		((2UL))
/** Source peripheral to destination peripheral - DMA control */
#define GPDMA_TRANSFERTYPE_P2P 		((3UL))

/** Burst size in Source and Destination definitions */
#define GPDMA_BSIZE_1 	((0UL)) /**< Burst size = 1 */
#define GPDMA_BSIZE_4 	((1UL)) /**< Burst size = 4 */
#define GPDMA_BSIZE_8 	((2UL)) /**< Burst size = 8 */
#define GPDMA_BSIZE_16 	((3UL)) /**< Burst size = 16 */
#define GPDMA_BSIZE_32 	((4UL)) /**< Burst size = 32 */
#define GPDMA_BSIZE_64 	((5UL)) /**< Burst size = 64 */
#define GPDMA_BSIZE_128 ((6UL)) /**< Burst size = 128 */
#define GPDMA_BSIZE_256 ((7UL)) /**< Burst size = 256 */

/** Width in Source transfer width and Destination transfer width definitions */
#define GPDMA_WIDTH_BYTE 		((0UL)) /**< Width = 1 byte */
#define GPDMA_WIDTH_HALFWORD 	((1UL)) /**< Width = 2 bytes */
#define GPDMA_WIDTH_WORD 		((2UL)) /**< Width = 4 bytes */

/** DMA Request Select Mode definitions */
#define GPDMA_REQSEL_UART 	((0UL)) /**< UART TX/RX is selected */
#define GPDMA_REQSEL_TIMER 	((1UL)) /**< Timer match is selected */

/**
 * @}
 */


/* Private Macros ------------------------------------------------------------- */
/** @defgroup GPDMA_Private_Macros GPDMA Private Macros
 * @{
 */

/* --------------------- BIT DEFINITIONS -------------------------------------- */
/*********************************************************************//**
 * Macro defines for DMA Interrupt Status register
 **********************************************************************/
#define GPDMA_DMACIntStat_Ch(n)			(((1UL<<n)&0xFF))
#define GPDMA_DMACIntStat_BITMASK		((0xFF))

/*********************************************************************//**
 * Macro defines for DMA Interrupt Terminal Count Request Status register
 **********************************************************************/
#define GPDMA_DMACIntTCStat_Ch(n)		(((1UL<<n)&0xFF))
#define GPDMA_DMACIntTCStat_BITMASK		((0xFF))

/*********************************************************************//**
 * Macro defines for DMA Interrupt Terminal Count Request Clear register
 **********************************************************************/
#define GPDMA_DMACIntTCClear_Ch(n)		(((1UL<<n)&0xFF))
#define GPDMA_DMACIntTCClear_BITMASK	((0xFF))

/*********************************************************************//**
 * Macro defines for DMA Interrupt Error Status register
 **********************************************************************/
#define GPDMA_DMACIntErrStat_Ch(n)		(((1UL<<n)&0xFF))
#define GPDMA_DMACIntErrStat_BITMASK	((0xFF))

/*********************************************************************//**
 * Macro defines for DMA Interrupt Error Clear register
 **********************************************************************/
#define GPDMA_DMACIntErrClr_Ch(n)		(((1UL<<n)&0xFF))
#define GPDMA_DMACIntErrClr_BITMASK		((0xFF))

/*********************************************************************//**
 * Macro defines for DMA Raw Interrupt Terminal Count Status register
 **********************************************************************/
#define GPDMA_DMACRawIntTCStat_Ch(n)	(((1UL<<n)&0xFF))
#define GPDMA_DMACRawIntTCStat_BITMASK	((0xFF))

/*********************************************************************//**
 * Macro defines for DMA Raw Error Interrupt Status register
 **********************************************************************/
#define GPDMA_DMACRawIntErrStat_Ch(n)	(((1UL<<n)&0xFF))
#define GPDMA_DMACRawIntErrStat_BITMASK	((0xFF))

/*********************************************************************//**
 * Macro defines for DMA Enabled Channel register
 **********************************************************************/
#define GPDMA_DMACEnbldChns_Ch(n)		(((1UL<<n)&0xFF))
#define GPDMA_DMACEnbldChns_BITMASK		((0xFF))

/*********************************************************************//**
 * Macro defines for DMA Software Burst Request register
 **********************************************************************/
#define	GPDMA_DMACSoftBReq_Src(n)		(((1UL<<n)&0xFFFF))
#define GPDMA_DMACSoftBReq_BITMASK		((0xFFFF))

/*********************************************************************//**
 * Macro defines for DMA Software Single Request register
 **********************************************************************/
#define GPDMA_DMACSoftSReq_Src(n) 		(((1UL<<n)&0xFFFF))
#define GPDMA_DMACSoftSReq_BITMASK		((0xFFFF))

/*********************************************************************//**
 * Macro defines for DMA Software Last Burst Request register
 **********************************************************************/
#define GPDMA_DMACSoftLBReq_Src(n)		(((1UL<<n)&0xFFFF))
#define GPDMA_DMACSoftLBReq_BITMASK		((0xFFFF))

/*********************************************************************//**
 * Macro defines for DMA Software Last Single Request register
 **********************************************************************/
#define GPDMA_DMACSoftLSReq_Src(n) 		(((1UL<<n)&0xFFFF))
#define GPDMA_DMACSoftLSReq_BITMASK		((0xFFFF))

/*********************************************************************//**
 * Macro defines for DMA Configuration register
 **********************************************************************/
#define GPDMA_DMACConfig_E				((0x01))	 /**< DMA Controller enable*/
#define GPDMA_DMACConfig_M				((0x02))	 /**< AHB Master endianness configuration*/
#define GPDMA_DMACConfig_BITMASK		((0x03))

/*********************************************************************//**
 * Macro defines for DMA Synchronization register
 **********************************************************************/
#define GPDMA_DMACSync_Src(n)			(((1UL<<n)&0xFFFF))
#define GPDMA_DMACSync_BITMASK			((0xFFFF))