📄 lpc177x_8x.h
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__O uint32_t NDDRIntSet;
__I uint32_t SysErrIntSt;
__O uint32_t SysErrIntClr;
__O uint32_t SysErrIntSet;
uint32_t RESERVED4[15];
union {
__I uint32_t I2C_RX; /* USB OTG I2C Registers */
__O uint32_t I2C_TX;
};
__IO uint32_t I2C_STS;
__IO uint32_t I2C_CTL;
__IO uint32_t I2C_CLKHI;
__O uint32_t I2C_CLKLO;
uint32_t RESERVED5[824];
union {
__IO uint32_t USBClkCtrl; /* USB Clock Control Registers */
__IO uint32_t OTGClkCtrl;
};
union {
__I uint32_t USBClkSt;
__I uint32_t OTGClkSt;
};
} LPC_USB_TypeDef;
/*------------- Ethernet Media Access Controller (EMAC) ----------------------*/
typedef struct
{
__IO uint32_t MAC1; /* MAC Registers */
__IO uint32_t MAC2;
__IO uint32_t IPGT;
__IO uint32_t IPGR;
__IO uint32_t CLRT;
__IO uint32_t MAXF;
__IO uint32_t SUPP;
__IO uint32_t TEST;
__IO uint32_t MCFG;
__IO uint32_t MCMD;
__IO uint32_t MADR;
__O uint32_t MWTD;
__I uint32_t MRDD;
__I uint32_t MIND;
uint32_t RESERVED0[2];
__IO uint32_t SA0;
__IO uint32_t SA1;
__IO uint32_t SA2;
uint32_t RESERVED1[45];
__IO uint32_t Command; /* Control Registers */
__I uint32_t Status;
__IO uint32_t RxDescriptor;
__IO uint32_t RxStatus;
__IO uint32_t RxDescriptorNumber;
__I uint32_t RxProduceIndex;
__IO uint32_t RxConsumeIndex;
__IO uint32_t TxDescriptor;
__IO uint32_t TxStatus;
__IO uint32_t TxDescriptorNumber;
__IO uint32_t TxProduceIndex;
__I uint32_t TxConsumeIndex;
uint32_t RESERVED2[10];
__I uint32_t TSV0;
__I uint32_t TSV1;
__I uint32_t RSV;
uint32_t RESERVED3[3];
__IO uint32_t FlowControlCounter;
__I uint32_t FlowControlStatus;
uint32_t RESERVED4[34];
__IO uint32_t RxFilterCtrl; /* Rx Filter Registers */
__I uint32_t RxFilterWoLStatus;
__O uint32_t RxFilterWoLClear;
uint32_t RESERVED5;
__IO uint32_t HashFilterL;
__IO uint32_t HashFilterH;
uint32_t RESERVED6[882];
__I uint32_t IntStatus; /* Module Control Registers */
__IO uint32_t IntEnable;
__O uint32_t IntClear;
__O uint32_t IntSet;
uint32_t RESERVED7;
__IO uint32_t PowerDown;
uint32_t RESERVED8;
__IO uint32_t Module_ID;
} LPC_EMAC_TypeDef;
/*------------- LCD controller (LCD) -----------------------------------------*/
typedef struct
{
__IO uint32_t TIMH; /* LCD Registers */
__IO uint32_t TIMV;
__IO uint32_t POL;
__IO uint32_t LE;
__IO uint32_t UPBASE;
__IO uint32_t LPBASE;
__IO uint32_t CTRL;
__IO uint32_t INTMSK;
__I uint32_t INTRAW;
__I uint32_t INTSTAT;
__O uint32_t INTCLR;
__I uint32_t UPCURR;
__I uint32_t LPCURR;
uint32_t RESERVED0[115];
__IO uint32_t PAL[128];
uint32_t RESERVED1[256];
__IO uint32_t CRSR_IMG[256];
__IO uint32_t CRSR_CTRL;
__IO uint32_t CRSR_CFG;
__IO uint32_t CRSR_PAL0;
__IO uint32_t CRSR_PAL1;
__IO uint32_t CRSR_XY;
__IO uint32_t CRSR_CLIP;
uint32_t RESERVED2[2];
__IO uint32_t CRSR_INTMSK;
__O uint32_t CRSR_INTCLR;
__I uint32_t CRSR_INTRAW;
__I uint32_t CRSR_INTSTAT;
} LPC_LCD_TypeDef;
/*------------- External Memory Controller (EMC) -----------------------------*/
typedef struct
{
__IO uint32_t Control;
__I uint32_t Status;
__IO uint32_t Config;
uint32_t RESERVED0[5];
__IO uint32_t DynamicControl;
__IO uint32_t DynamicRefresh;
__IO uint32_t DynamicReadConfig;
uint32_t RESERVED1[1];
__IO uint32_t DynamicRP;
__IO uint32_t DynamicRAS;
__IO uint32_t DynamicSREX;
__IO uint32_t DynamicAPR;
__IO uint32_t DynamicDAL;
__IO uint32_t DynamicWR;
__IO uint32_t DynamicRC;
__IO uint32_t DynamicRFC;
__IO uint32_t DynamicXSR;
__IO uint32_t DynamicRRD;
__IO uint32_t DynamicMRD;
uint32_t RESERVED2[9];
__IO uint32_t StaticExtendedWait;
uint32_t RESERVED3[31];
__IO uint32_t DynamicConfig0;
__IO uint32_t DynamicRasCas0;
uint32_t RESERVED4[6];
__IO uint32_t DynamicConfig1;
__IO uint32_t DynamicRasCas1;
uint32_t RESERVED5[6];
__IO uint32_t DynamicConfig2;
__IO uint32_t DynamicRasCas2;
uint32_t RESERVED6[6];
__IO uint32_t DynamicConfig3;
__IO uint32_t DynamicRasCas3;
uint32_t RESERVED7[38];
__IO uint32_t StaticConfig0;
__IO uint32_t StaticWaitWen0;
__IO uint32_t StaticWaitOen0;
__IO uint32_t StaticWaitRd0;
__IO uint32_t StaticWaitPage0;
__IO uint32_t StaticWaitWr0;
__IO uint32_t StaticWaitTurn0;
uint32_t RESERVED8[1];
__IO uint32_t StaticConfig1;
__IO uint32_t StaticWaitWen1;
__IO uint32_t StaticWaitOen1;
__IO uint32_t StaticWaitRd1;
__IO uint32_t StaticWaitPage1;
__IO uint32_t StaticWaitWr1;
__IO uint32_t StaticWaitTurn1;
uint32_t RESERVED9[1];
__IO uint32_t StaticConfig2;
__IO uint32_t StaticWaitWen2;
__IO uint32_t StaticWaitOen2;
__IO uint32_t StaticWaitRd2;
__IO uint32_t StaticWaitPage2;
__IO uint32_t StaticWaitWr2;
__IO uint32_t StaticWaitTurn2;
uint32_t RESERVED10[1];
__IO uint32_t StaticConfig3;
__IO uint32_t StaticWaitWen3;
__IO uint32_t StaticWaitOen3;
__IO uint32_t StaticWaitRd3;
__IO uint32_t StaticWaitPage3;
__IO uint32_t StaticWaitWr3;
__IO uint32_t StaticWaitTurn3;
} LPC_EMC_TypeDef;
/*------------- CRC Engine (CRC) -----------------------------------------*/
typedef struct
{
__IO uint32_t MODE;
__IO uint32_t SEED;
union {
__I uint32_t SUM;
__O uint32_t WR_DATA_DWORD;
__O uint16_t WR_DATA_WORD;
uint16_t RESERVED_WORD;
__O uint8_t WR_DATA_BYTE;
uint8_t RESERVED_BYTE[3];
};
} LPC_CRC_TypeDef;
/*------------- EEPROM Controller (EEPROM) -----------------------------------*/
typedef struct
{
__IO uint32_t CMD; /* 0x0080 */
__IO uint32_t ADDR;
__IO uint32_t WDATA;
__IO uint32_t RDATA;
__IO uint32_t WSTATE; /* 0x0090 */
__IO uint32_t CLKDIV;
__IO uint32_t PWRDWN; /* 0x0098 */
uint32_t RESERVED0[975];
__IO uint32_t INT_CLR_ENABLE; /* 0x0FD8 */
__IO uint32_t INT_SET_ENABLE;
__IO uint32_t INT_STATUS; /* 0x0FE0 */
__IO uint32_t INT_ENABLE;
__IO uint32_t INT_CLR_STATUS;
__IO uint32_t INT_SET_STATUS;
} LPC_EEPROM_TypeDef;
#if defined ( __CC_ARM )
#pragma no_anon_unions
#endif
/******************************************************************************/
/* Peripheral memory map */
/******************************************************************************/
/* Base addresses */
#define LPC_FLASH_BASE (0x00000000UL)
#define LPC_RAM_BASE (0x10000000UL)
#define LPC_PERI_RAM_BASE (0x20000000UL)
#define LPC_APB0_BASE (0x40000000UL)
#define LPC_APB1_BASE (0x40080000UL)
#define LPC_AHBRAM1_BASE (0x20004000UL)
#define LPC_AHB_BASE (0x20080000UL)
#define LPC_CM3_BASE (0xE0000000UL)
/* APB0 peripherals */
#define LPC_WDT_BASE (LPC_APB0_BASE + 0x00000)
#define LPC_TIM0_BASE (LPC_APB0_BASE + 0x04000)
#define LPC_TIM1_BASE (LPC_APB0_BASE + 0x08000)
#define LPC_UART0_BASE (LPC_APB0_BASE + 0x0C000)
#define LPC_UART1_BASE (LPC_APB0_BASE + 0x10000)
#define LPC_PWM0_BASE (LPC_APB0_BASE + 0x14000)
#define LPC_PWM1_BASE (LPC_APB0_BASE + 0x18000)
#define LPC_I2C0_BASE (LPC_APB0_BASE + 0x1C000)
#define LPC_RTC_BASE (LPC_APB0_BASE + 0x24000)
#define LPC_GPIOINT_BASE (LPC_APB0_BASE + 0x28080)
#define LPC_IOCON_BASE (LPC_APB0_BASE + 0x2C000)
#define LPC_SSP1_BASE (LPC_APB0_BASE + 0x30000)
#define LPC_ADC_BASE (LPC_APB0_BASE + 0x34000)
#define LPC_CANAF_RAM_BASE (LPC_APB0_BASE + 0x38000)
#define LPC_CANAF_BASE (LPC_APB0_BASE + 0x3C000)
#define LPC_CANCR_BASE (LPC_APB0_BASE + 0x40000)
#define LPC_CAN1_BASE (LPC_APB0_BASE + 0x44000)
#define LPC_CAN2_BASE (LPC_APB0_BASE + 0x48000)
#define LPC_I2C1_BASE (LPC_APB0_BASE + 0x5C000)
/* APB1 peripherals */
#define LPC_SSP0_BASE (LPC_APB1_BASE + 0x08000)
#define LPC_DAC_BASE (LPC_APB1_BASE + 0x0C000)
#define LPC_TIM2_BASE (LPC_APB1_BASE + 0x10000)
#define LPC_TIM3_BASE (LPC_APB1_BASE + 0x14000)
#define LPC_UART2_BASE (LPC_APB1_BASE + 0x18000)
#define LPC_UART3_BASE (LPC_APB1_BASE + 0x1C000)
#define LPC_I2C2_BASE (LPC_APB1_BASE + 0x20000)
#define LPC_UART4_BASE (LPC_APB1_BASE + 0x24000)
#define LPC_I2S_BASE (LPC_APB1_BASE + 0x28000)
#define LPC_SSP2_BASE (LPC_APB1_BASE + 0x2C000)
#define LPC_MCPWM_BASE (LPC_APB1_BASE + 0x38000)
#define LPC_QEI_BASE (LPC_APB1_BASE + 0x3C000)
#define LPC_MCI_BASE (LPC_APB1_BASE + 0x40000)
#define LPC_SC_BASE (LPC_APB1_BASE + 0x7C000)
/* AHB peripherals */
#define LPC_GPDMA_BASE (LPC_AHB_BASE + 0x00000)
#define LPC_GPDMACH0_BASE (LPC_AHB_BASE + 0x00100)
#define LPC_GPDMACH1_BASE (LPC_AHB_BASE + 0x00120)
#define LPC_GPDMACH2_BASE (LPC_AHB_BASE + 0x00140)
#define LPC_GPDMACH3_BASE (LPC_AHB_BASE + 0x00160)
#define LPC_GPDMACH4_BASE (LPC_AHB_BASE + 0x00180)
#define LPC_GPDMACH5_BASE (LPC_AHB_BASE + 0x001A0)
#define LPC_GPDMACH6_BASE (LPC_AHB_BASE + 0x001C0)
#define LPC_GPDMACH7_BASE (LPC_AHB_BASE + 0x001E0)
#define LPC_EMAC_BASE (LPC_AHB_BASE + 0x04000)
#define LPC_LCD_BASE (LPC_AHB_BASE + 0x08000)
#define LPC_USB_BASE (LPC_AHB_BASE + 0x0C000)
#define LPC_CRC_BASE (LPC_AHB_BASE + 0x10000)
#define LPC_GPIO0_BASE (LPC_AHB_BASE + 0x18000)
#define LPC_GPIO1_BASE (LPC_AHB_BASE + 0x18020)
#define LPC_GPIO2_BASE (LPC_AHB_BASE + 0x18040)
#define LPC_GPIO3_BASE (LPC_AHB_BASE + 0x18060)
#define LPC_GPIO4_BASE (LPC_AHB_BASE + 0x18080)
#define LPC_GPIO5_BASE (LPC_AHB_BASE + 0x180A0)
#define LPC_EMC_BASE (LPC_AHB_BASE + 0x1C000)
#define LPC_EEPROM_BASE (LPC_FLASH_BASE+ 0x200080)
/******************************************************************************/
/* Peripheral declaration */
/******************************************************************************/
#define LPC_SC ((LPC_SC_TypeDef *) LPC_SC_BASE )
#define LPC_WDT ((LPC_WDT_TypeDef *) LPC_WDT_BASE )
#define LPC_TIM0 ((LPC_TIM_TypeDef *) LPC_TIM0_BASE )
#define LPC_TIM1 ((LPC_TIM_TypeDef *) LPC_TIM1_BASE )
#define LPC_TIM2 ((LPC_TIM_TypeDef *) LPC_TIM2_BASE )
#define LPC_TIM3 ((LPC_TIM_TypeDef *) LPC_TIM3_BASE )
#define LPC_UART0 ((LPC_UART_TypeDef *) LPC_UART0_BASE )
#define LPC_UART1 ((LPC_UART1_TypeDef *) LPC_UART1_BASE )
#define LPC_UART2 ((LPC_UART_TypeDef *) LPC_UART2_BASE )
#define LPC_UART3 ((LPC_UART_TypeDef *) LPC_UART3_BASE )
#define LPC_UART4 ((LPC_UART4_TypeDef *) LPC_UART4_BASE )
#define LPC_PWM0 ((LPC_PWM_TypeDef *) LPC_PWM0_BASE )
#define LPC_PWM1 ((LPC_PWM_TypeDef *) LPC_PWM1_BASE )
#define LPC_I2C0 ((LPC_I2C_TypeDef *) LPC_I2C0_BASE )
#define LPC_I2C1 ((LPC_I2C_TypeDef *) LPC_I2C1_BASE )
#define LPC_I2C2 ((LPC_I2C_TypeDef *) LPC_I2C2_BASE )
#define LPC_I2S ((LPC_I2S_TypeDef *) LPC_I2S_BASE )
#define LPC_RTC ((LPC_RTC_TypeDef *) LPC_RTC_BASE )
#define LPC_GPIOINT ((LPC_GPIOINT_TypeDef *) LPC_GPIOINT_BASE )
#define LPC_IOCON ((LPC_IOCON_TypeDef *) LPC_IOCON_BASE )
#define LPC_SSP0 ((LPC_SSP_TypeDef *) LPC_SSP0_BASE )
#define LPC_SSP1 ((LPC_SSP_TypeDef *) LPC_SSP1_BASE )
#define LPC_SSP2 ((LPC_SSP_TypeDef *) LPC_SSP2_BASE )
#define LPC_ADC ((LPC_ADC_TypeDef *) LPC_ADC_BASE )
#define LPC_DAC ((LPC_DAC_TypeDef *) LPC_DAC_BASE )
#define LPC_CANAF_RAM ((LPC_CANAF_RAM_TypeDef *) LPC_CANAF_RAM_BASE)
#define LPC_CANAF ((LPC_CANAF_TypeDef *) LPC_CANAF_BASE )
#define LPC_CANCR ((LPC_CANCR_TypeDef *) LPC_CANCR_BASE )
#define LPC_CAN1 ((LPC_CAN_TypeDef *) LPC_CAN1_BASE )
#define LPC_CAN2 ((LPC_CAN_TypeDef *) LPC_CAN2_BASE )
#define LPC_MCPWM ((LPC_MCPWM_TypeDef *) LPC_MCPWM_BASE )
#define LPC_QEI ((LPC_QEI_TypeDef *) LPC_QEI_BASE )
#define LPC_MCI ((LPC_MCI_TypeDef *) LPC_MCI_BASE )
#define LPC_GPDMA ((LPC_GPDMA_TypeDef *) LPC_GPDMA_BASE )
#define LPC_GPDMACH0 ((LPC_GPDMACH_TypeDef *) LPC_GPDMACH0_BASE )
#define LPC_GPDMACH1 ((LPC_GPDMACH_TypeDef *) LPC_GPDMACH1_BASE )
#define LPC_GPDMACH2 ((LPC_GPDMACH_TypeDef *) LPC_GPDMACH2_BASE )
#define LPC_GPDMACH3 ((LPC_GPDMACH_TypeDef *) LPC_GPDMACH3_BASE )
#define LPC_GPDMACH4 ((LPC_GPDMACH_TypeDef *) LPC_GPDMACH4_BASE )
#define LPC_GPDMACH5 ((LPC_GPDMACH_TypeDef *) LPC_GPDMACH5_BASE )
#define LPC_GPDMACH6 ((LPC_GPDMACH_TypeDef *) LPC_GPDMACH6_BASE )
#define LPC_GPDMACH7 ((LPC_GPDMACH_TypeDef *) LPC_GPDMACH7_BASE )
#define LPC_EMAC ((LPC_EMAC_TypeDef *) LPC_EMAC_BASE )
#define LPC_LCD ((LPC_LCD_TypeDef *) LPC_LCD_BASE )
#define LPC_USB ((LPC_USB_TypeDef *) LPC_USB_BASE )
#define LPC_GPIO0 ((LPC_GPIO_TypeDef *) LPC_GPIO0_BASE )
#define LPC_GPIO1 ((LPC_GPIO_TypeDef *) LPC_GPIO1_BASE )
#define LPC_GPIO2 ((LPC_GPIO_TypeDef *) LPC_GPIO2_BASE )
#define LPC_GPIO3 ((LPC_GPIO_TypeDef *) LPC_GPIO3_BASE )
#define LPC_GPIO4 ((LPC_GPIO_TypeDef *) LPC_GPIO4_BASE )
#define LPC_GPIO5 ((LPC_GPIO_TypeDef *) LPC_GPIO5_BASE )
#define LPC_EMC ((LPC_EMC_TypeDef *) LPC_EMC_BASE )
#define LPC_CRC ((LPC_CRC_TypeDef *) LPC_CRC_BASE )
#define LPC_EEPROM ((LPC_EEPROM_TypeDef *) LPC_EEPROM_BASE )
#endif // __LPC177x_8x_H__
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