📄 lpc177x_8x.h
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__IO uint32_t ERLASTSTAMP1;
__IO uint32_t ERLASTSTAMP2;
} LPC_RTC_TypeDef;
/*------------- Watchdog Timer (WDT) -----------------------------------------*/
typedef struct
{
__IO uint8_t MOD;
uint8_t RESERVED0[3];
__IO uint32_t TC;
__O uint8_t FEED;
uint8_t RESERVED1[3];
__I uint32_t TV;
uint32_t RESERVED2;
__IO uint32_t WARNINT;
__IO uint32_t WINDOW;
} LPC_WDT_TypeDef;
/*------------- Analog-to-Digital Converter (ADC) ----------------------------*/
typedef struct
{
__IO uint32_t CR; /*!< Offset: 0x000 A/D Control Register (R/W) */
__IO uint32_t GDR; /*!< Offset: 0x004 A/D Global Data Register (R/W) */
uint32_t RESERVED0;
__IO uint32_t INTEN; /*!< Offset: 0x00C A/D Interrupt Enable Register (R/W) */
__IO uint32_t DR[8]; /*!< Offset: 0x010-0x02C A/D Channel 0..7 Data Register (R/W) */
__I uint32_t STAT; /*!< Offset: 0x030 A/D Status Register (R/ ) */
__IO uint32_t ADTRM;
} LPC_ADC_TypeDef;
/*------------- Digital-to-Analog Converter (DAC) ----------------------------*/
typedef struct
{
__IO uint32_t CR;
__IO uint32_t CTRL;
__IO uint32_t CNTVAL;
} LPC_DAC_TypeDef;
/*------------- Motor Control Pulse-Width Modulation (MCPWM) -----------------*/
typedef struct
{
__I uint32_t CON;
__O uint32_t CON_SET;
__O uint32_t CON_CLR;
__I uint32_t CAPCON;
__O uint32_t CAPCON_SET;
__O uint32_t CAPCON_CLR;
__IO uint32_t TC0;
__IO uint32_t TC1;
__IO uint32_t TC2;
__IO uint32_t LIM0;
__IO uint32_t LIM1;
__IO uint32_t LIM2;
__IO uint32_t MAT0;
__IO uint32_t MAT1;
__IO uint32_t MAT2;
__IO uint32_t DT;
__IO uint32_t CP;
__IO uint32_t CAP0;
__IO uint32_t CAP1;
__IO uint32_t CAP2;
__I uint32_t INTEN;
__O uint32_t INTEN_SET;
__O uint32_t INTEN_CLR;
__I uint32_t CNTCON;
__O uint32_t CNTCON_SET;
__O uint32_t CNTCON_CLR;
__I uint32_t INTF;
__O uint32_t INTF_SET;
__O uint32_t INTF_CLR;
__O uint32_t CAP_CLR;
} LPC_MCPWM_TypeDef;
/*------------- Quadrature Encoder Interface (QEI) ---------------------------*/
typedef struct
{
__O uint32_t CON;
__I uint32_t STAT;
__IO uint32_t CONF;
__I uint32_t POS;
__IO uint32_t MAXPOS;
__IO uint32_t CMPOS0;
__IO uint32_t CMPOS1;
__IO uint32_t CMPOS2;
__I uint32_t INXCNT;
__IO uint32_t INXCMP0;
__IO uint32_t LOAD;
__I uint32_t TIME;
__I uint32_t VEL;
__I uint32_t CAP;
__IO uint32_t VELCOMP;
__IO uint32_t FILTERPHA;
__IO uint32_t FILTERPHB;
__IO uint32_t FILTERINX;
__IO uint32_t WINDOW;
__IO uint32_t INXCMP1;
__IO uint32_t INXCMP2;
uint32_t RESERVED0[993];
__O uint32_t IEC;
__O uint32_t IES;
__I uint32_t INTSTAT;
__I uint32_t IE;
__O uint32_t CLR;
__O uint32_t SET;
} LPC_QEI_TypeDef;
/*------------- SD/MMC card Interface (MCI)-----------------------------------*/
typedef struct
{
__IO uint32_t POWER;
__IO uint32_t CLOCK;
__IO uint32_t ARGUMENT;
__IO uint32_t COMMAND;
__I uint32_t RESP_CMD;
__I uint32_t RESP0;
__I uint32_t RESP1;
__I uint32_t RESP2;
__I uint32_t RESP3;
__IO uint32_t DATATMR;
__IO uint32_t DATALEN;
__IO uint32_t DATACTRL;
__I uint32_t DATACNT;
__I uint32_t STATUS;
__O uint32_t CLEAR;
__IO uint32_t MASK0;
uint32_t RESERVED0[2];
__I uint32_t FIFOCNT;
uint32_t RESERVED1[13];
__IO uint32_t FIFO;
} LPC_MCI_TypeDef;
/*------------- Controller Area Network (CAN) --------------------------------*/
typedef struct
{
__IO uint32_t mask[512]; /* ID Masks */
} LPC_CANAF_RAM_TypeDef;
typedef struct /* Acceptance Filter Registers */
{
///Offset: 0x00000000 - Acceptance Filter Register
__IO uint32_t AFMR;
///Offset: 0x00000004 - Standard Frame Individual Start Address Register
__IO uint32_t SFF_sa;
///Offset: 0x00000008 - Standard Frame Group Start Address Register
__IO uint32_t SFF_GRP_sa;
///Offset: 0x0000000C - Extended Frame Start Address Register
__IO uint32_t EFF_sa;
///Offset: 0x00000010 - Extended Frame Group Start Address Register
__IO uint32_t EFF_GRP_sa;
///Offset: 0x00000014 - End of AF Tables register
__IO uint32_t ENDofTable;
///Offset: 0x00000018 - LUT Error Address register
__I uint32_t LUTerrAd;
///Offset: 0x0000001C - LUT Error Register
__I uint32_t LUTerr;
///Offset: 0x00000020 - CAN Central Transmit Status Register
__IO uint32_t FCANIE;
///Offset: 0x00000024 - FullCAN Interrupt and Capture registers 0
__IO uint32_t FCANIC0;
///Offset: 0x00000028 - FullCAN Interrupt and Capture registers 1
__IO uint32_t FCANIC1;
} LPC_CANAF_TypeDef;
typedef struct /* Central Registers */
{
__I uint32_t TxSR;
__I uint32_t RxSR;
__I uint32_t MSR;
} LPC_CANCR_TypeDef;
typedef struct /* Controller Registers */
{
///Offset: 0x00000000 - Controls the operating mode of the CAN Controller
__IO uint32_t MOD;
///Offset: 0x00000004 - Command bits that affect the state
__O uint32_t CMR;
///Offset: 0x00000008 - Global Controller Status and Error Counters
__IO uint32_t GSR;
///Offset: 0x0000000C - Interrupt status, Arbitration Lost Capture, Error Code Capture
__I uint32_t ICR;
///Offset: 0x00000010 - Interrupt Enable Register
__IO uint32_t IER;
///Offset: 0x00000014 - Bus Timing Register
__IO uint32_t BTR;
///Offset: 0x00000018 - Error Warning Limit
__IO uint32_t EWL;
///Offset: 0x0000001C - Status Register
__I uint32_t SR;
///Offset: 0x00000020 - Receive frame status
__IO uint32_t RFS;
///Offset: 0x00000024 - Received Identifier
__IO uint32_t RID;
///Offset: 0x00000028 - Received data bytes 1-4
__IO uint32_t RDA;
///Offset: 0x0000002C - Received data bytes 5-8
__IO uint32_t RDB;
///Offset: 0x00000030 - Transmit frame info (Tx Buffer 1)
__IO uint32_t TFI1;
///Offset: 0x00000034 - Transmit Identifier (Tx Buffer 1)
__IO uint32_t TID1;
///Offset: 0x00000038 - Transmit data bytes 1-4 (Tx Buffer 1)
__IO uint32_t TDA1;
///Offset: 0x0000003C - Transmit data bytes 5-8 (Tx Buffer 1)
__IO uint32_t TDB1;
///Offset: 0x00000040 - Transmit frame info (Tx Buffer 2)
__IO uint32_t TFI2;
///Offset: 0x00000044 - Transmit Identifier (Tx Buffer 2)
__IO uint32_t TID2;
///Offset: 0x00000048 - Transmit data bytes 1-4 (Tx Buffer 2)
__IO uint32_t TDA2;
///Offset: 0x0000004C - Transmit data bytes 5-8 (Tx Buffer 2)
__IO uint32_t TDB2;
///Offset: 0x00000050 - Transmit frame info (Tx Buffer 3)
__IO uint32_t TFI3;
///Offset: 0x00000054 - Transmit Identifier (Tx Buffer 3)
__IO uint32_t TID3;
///Offset: 0x00000058 - Transmit data bytes 1-4 (Tx Buffer 3)
__IO uint32_t TDA3;
///Offset: 0x0000005C - Transmit data bytes 5-8 (Tx Buffer 3)
__IO uint32_t TDB3;
} LPC_CAN_TypeDef;
/*------------- General Purpose Direct Memory Access (GPDMA) -----------------*/
typedef struct /* Common Registers */
{
__I uint32_t IntStat;
__I uint32_t IntTCStat;
__O uint32_t IntTCClear;
__I uint32_t IntErrStat;
__O uint32_t IntErrClr;
__I uint32_t RawIntTCStat;
__I uint32_t RawIntErrStat;
__I uint32_t EnbldChns;
__IO uint32_t SoftBReq;
__IO uint32_t SoftSReq;
__IO uint32_t SoftLBReq;
__IO uint32_t SoftLSReq;
__IO uint32_t Config;
__IO uint32_t Sync;
} LPC_GPDMA_TypeDef;
typedef struct /* Channel Registers */
{
__IO uint32_t CSrcAddr;
__IO uint32_t CDestAddr;
__IO uint32_t CLLI;
__IO uint32_t CControl;
__IO uint32_t CConfig;
} LPC_GPDMACH_TypeDef;
/*------------- Universal Serial Bus (USB) -----------------------------------*/
typedef struct
{
__I uint32_t Revision; /* USB Host Registers */
__IO uint32_t Control;
__IO uint32_t CommandStatus;
__IO uint32_t InterruptStatus;
__IO uint32_t InterruptEnable;
__IO uint32_t InterruptDisable;
__IO uint32_t HCCA;
__I uint32_t PeriodCurrentED;
__IO uint32_t ControlHeadED;
__IO uint32_t ControlCurrentED;
__IO uint32_t BulkHeadED;
__IO uint32_t BulkCurrentED;
__I uint32_t DoneHead;
__IO uint32_t FmInterval;
__I uint32_t FmRemaining;
__I uint32_t FmNumber;
__IO uint32_t PeriodicStart;
__IO uint32_t LSTreshold;
__IO uint32_t RhDescriptorA;
__IO uint32_t RhDescriptorB;
__IO uint32_t RhStatus;
__IO uint32_t RhPortStatus1;
__IO uint32_t RhPortStatus2;
uint32_t RESERVED0[40];
__I uint32_t Module_ID;
__I uint32_t IntSt; /* USB On-The-Go Registers */
__IO uint32_t IntEn;
__O uint32_t IntSet;
__O uint32_t IntClr;
__IO uint32_t StCtrl;
__IO uint32_t Tmr;
uint32_t RESERVED1[58];
__I uint32_t DevIntSt; /* USB Device Interrupt Registers */
__IO uint32_t DevIntEn;
__O uint32_t DevIntClr;
__O uint32_t DevIntSet;
__O uint32_t CmdCode; /* USB Device SIE Command Registers */
__I uint32_t CmdData;
__I uint32_t RxData; /* USB Device Transfer Registers */
__O uint32_t TxData;
__I uint32_t RxPLen;
__O uint32_t TxPLen;
__IO uint32_t Ctrl;
__O uint32_t DevIntPri;
__I uint32_t EpIntSt; /* USB Device Endpoint Interrupt Regs */
__IO uint32_t EpIntEn;
__O uint32_t EpIntClr;
__O uint32_t EpIntSet;
__O uint32_t EpIntPri;
__IO uint32_t ReEp; /* USB Device Endpoint Realization Reg*/
__O uint32_t EpInd;
__IO uint32_t MaxPSize;
__I uint32_t DMARSt; /* USB Device DMA Registers */
__O uint32_t DMARClr;
__O uint32_t DMARSet;
uint32_t RESERVED2[9];
__IO uint32_t UDCAH;
__I uint32_t EpDMASt;
__O uint32_t EpDMAEn;
__O uint32_t EpDMADis;
__I uint32_t DMAIntSt;
__IO uint32_t DMAIntEn;
uint32_t RESERVED3[2];
__I uint32_t EoTIntSt;
__O uint32_t EoTIntClr;
__O uint32_t EoTIntSet;
__I uint32_t NDDRIntSt;
__O uint32_t NDDRIntClr;
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