📄 lpc177x_8x.h
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__IO uint32_t SET;
__O uint32_t CLR;
} LPC_GPIO_TypeDef;
typedef struct
{
__I uint32_t IntStatus;
__I uint32_t IO0IntStatR;
__I uint32_t IO0IntStatF;
__O uint32_t IO0IntClr;
__IO uint32_t IO0IntEnR;
__IO uint32_t IO0IntEnF;
uint32_t RESERVED0[3];
__I uint32_t IO2IntStatR;
__I uint32_t IO2IntStatF;
__O uint32_t IO2IntClr;
__IO uint32_t IO2IntEnR;
__IO uint32_t IO2IntEnF;
} LPC_GPIOINT_TypeDef;
/*------------- Timer (TIM) --------------------------------------------------*/
typedef struct
{
__IO uint32_t IR; /*!< Offset: 0x000 Interrupt Register (R/W) */
__IO uint32_t TCR; /*!< Offset: 0x004 Timer Control Register (R/W) */
__IO uint32_t TC; /*!< Offset: 0x008 Timer Counter Register (R/W) */
__IO uint32_t PR; /*!< Offset: 0x00C Prescale Register (R/W) */
__IO uint32_t PC; /*!< Offset: 0x010 Prescale Counter Register (R/W) */
__IO uint32_t MCR; /*!< Offset: 0x014 Match Control Register (R/W) */
__IO uint32_t MR0; /*!< Offset: 0x018 Match Register 0 (R/W) */
__IO uint32_t MR1; /*!< Offset: 0x01C Match Register 1 (R/W) */
__IO uint32_t MR2; /*!< Offset: 0x020 Match Register 2 (R/W) */
__IO uint32_t MR3; /*!< Offset: 0x024 Match Register 3 (R/W) */
__IO uint32_t CCR; /*!< Offset: 0x028 Capture Control Register (R/W) */
__I uint32_t CR0; /*!< Offset: 0x02C Capture Register 0 (R/ ) */
__I uint32_t CR1; /*!< Offset: 0x030 Capture Register 1 (R/ ) */
uint32_t RESERVED0[2];
__IO uint32_t EMR; /*!< Offset: 0x03C External Match Register (R/W) */
uint32_t RESERVED1[12];
__IO uint32_t CTCR; /*!< Offset: 0x070 Count Control Register (R/W) */
} LPC_TIM_TypeDef;
/*------------- Pulse-Width Modulation (PWM) ---------------------------------*/
typedef struct
{
__IO uint32_t IR; /*!< Offset: 0x000 Interrupt Register (R/W) */
__IO uint32_t TCR; /*!< Offset: 0x004 Timer Control Register (R/W) */
__IO uint32_t TC; /*!< Offset: 0x008 Timer Counter Register (R/W) */
__IO uint32_t PR; /*!< Offset: 0x00C Prescale Register (R/W) */
__IO uint32_t PC; /*!< Offset: 0x010 Prescale Counter Register (R/W) */
__IO uint32_t MCR; /*!< Offset: 0x014 Match Control Register (R/W) */
__IO uint32_t MR0; /*!< Offset: 0x018 Match Register 0 (R/W) */
__IO uint32_t MR1; /*!< Offset: 0x01C Match Register 1 (R/W) */
__IO uint32_t MR2; /*!< Offset: 0x020 Match Register 2 (R/W) */
__IO uint32_t MR3; /*!< Offset: 0x024 Match Register 3 (R/W) */
__IO uint32_t CCR; /*!< Offset: 0x028 Capture Control Register (R/W) */
__I uint32_t CR0; /*!< Offset: 0x02C Capture Register 0 (R/ ) */
__I uint32_t CR1; /*!< Offset: 0x030 Capture Register 1 (R/ ) */
__I uint32_t CR2; /*!< Offset: 0x034 Capture Register 2 (R/ ) */
__I uint32_t CR3; /*!< Offset: 0x038 Capture Register 3 (R/ ) */
uint32_t RESERVED0;
__IO uint32_t MR4; /*!< Offset: 0x040 Match Register 4 (R/W) */
__IO uint32_t MR5; /*!< Offset: 0x044 Match Register 5 (R/W) */
__IO uint32_t MR6; /*!< Offset: 0x048 Match Register 6 (R/W) */
__IO uint32_t PCR; /*!< Offset: 0x04C PWM Control Register (R/W) */
__IO uint32_t LER; /*!< Offset: 0x050 Load Enable Register (R/W) */
uint32_t RESERVED1[7];
__IO uint32_t CTCR; /*!< Offset: 0x070 Counter Control Register (R/W) */
} LPC_PWM_TypeDef;
/*------------- Universal Asynchronous Receiver Transmitter (UARTx) -----------*/
/* There are three types of UARTs on the chip:
(1) UART0,UART2, and UART3 are the standard UART.
(2) UART1 is the standard with modem capability.
(3) USART(UART4) is the sync/async UART with smart card capability.
More details can be found on the Users Manual. */
#if 0
typedef struct
{
union {
__I uint8_t RBR;
__O uint8_t THR;
__IO uint8_t DLL;
uint32_t RESERVED0;
};
union {
__IO uint8_t DLM;
__IO uint32_t IER;
};
union {
__I uint32_t IIR;
__O uint8_t FCR;
};
__IO uint8_t LCR;
uint8_t RESERVED1[7];
__I uint8_t LSR;
uint8_t RESERVED2[7];
__IO uint8_t SCR;
uint8_t RESERVED3[3];
__IO uint32_t ACR;
__IO uint8_t ICR;
uint8_t RESERVED4[3];
__IO uint8_t FDR;
uint8_t RESERVED5[7];
__IO uint8_t TER;
uint8_t RESERVED6[39];
__I uint8_t FIFOLVL;
} LPC_UART_TypeDef;
#else
typedef struct
{
union
{
__I uint8_t RBR;
__O uint8_t THR;
__IO uint8_t DLL;
uint32_t RESERVED0;
};
union
{
__IO uint8_t DLM;
__IO uint32_t IER;
};
union
{
__I uint32_t IIR;
__O uint8_t FCR;
};
__IO uint8_t LCR;
uint8_t RESERVED1[7];//Reserved
__I uint8_t LSR;
uint8_t RESERVED2[7];//Reserved
__IO uint8_t SCR;
uint8_t RESERVED3[3];//Reserved
__IO uint32_t ACR;
__IO uint8_t ICR;
uint8_t RESERVED4[3];//Reserved
__IO uint8_t FDR;
uint8_t RESERVED5[7];//Reserved
__IO uint8_t TER;
uint8_t RESERVED8[27];//Reserved
__IO uint8_t RS485CTRL;
uint8_t RESERVED9[3];//Reserved
__IO uint8_t ADRMATCH;
uint8_t RESERVED10[3];//Reserved
__IO uint8_t RS485DLY;
uint8_t RESERVED11[3];//Reserved
__I uint8_t FIFOLVL;
}LPC_UART_TypeDef;
#endif
typedef struct
{
union {
__I uint8_t RBR;
__O uint8_t THR;
__IO uint8_t DLL;
uint32_t RESERVED0;
};
union {
__IO uint8_t DLM;
__IO uint32_t IER;
};
union {
__I uint32_t IIR;
__O uint8_t FCR;
};
__IO uint8_t LCR;
uint8_t RESERVED1[3];
__IO uint8_t MCR;
uint8_t RESERVED2[3];
__I uint8_t LSR;
uint8_t RESERVED3[3];
__I uint8_t MSR;
uint8_t RESERVED4[3];
__IO uint8_t SCR;
uint8_t RESERVED5[3];
__IO uint32_t ACR;
uint32_t RESERVED6;
__IO uint32_t FDR;
uint32_t RESERVED7;
__IO uint8_t TER;
uint8_t RESERVED8[27];
__IO uint8_t RS485CTRL;
uint8_t RESERVED9[3];
__IO uint8_t ADRMATCH;
uint8_t RESERVED10[3];
__IO uint8_t RS485DLY;
uint8_t RESERVED11[3];
__I uint8_t FIFOLVL;
} LPC_UART1_TypeDef;
typedef struct
{
union {
__I uint32_t RBR; /*!< Offset: 0x000 Receiver Buffer Register (R/ ) */
__O uint32_t THR; /*!< Offset: 0x000 Transmit Holding Register ( /W) */
__IO uint32_t DLL; /*!< Offset: 0x000 Divisor Latch LSB (R/W) */
};
union {
__IO uint32_t DLM; /*!< Offset: 0x004 Divisor Latch MSB (R/W) */
__IO uint32_t IER; /*!< Offset: 0x000 Interrupt Enable Register (R/W) */
};
union {
__I uint32_t IIR; /*!< Offset: 0x008 Interrupt ID Register (R/ ) */
__O uint32_t FCR; /*!< Offset: 0x008 FIFO Control Register ( /W) */
};
__IO uint32_t LCR; /*!< Offset: 0x00C Line Control Register (R/W) */
__IO uint32_t MCR; /*!< Offset: 0x010 Modem control Register (R/W) */
__I uint32_t LSR; /*!< Offset: 0x014 Line Status Register (R/ ) */
__I uint32_t MSR; /*!< Offset: 0x018 Modem status Register (R/ ) */
__IO uint32_t SCR; /*!< Offset: 0x01C Scratch Pad Register (R/W) */
__IO uint32_t ACR; /*!< Offset: 0x020 Auto-baud Control Register (R/W) */
__IO uint32_t ICR; /*!< Offset: 0x024 irDA Control Register (R/W) */
__IO uint32_t FDR; /*!< Offset: 0x028 Fractional Divider Register (R/W) */
__IO uint32_t OSR; /*!< Offset: 0x02C Over sampling Register (R/W) */
__O uint32_t POP; /*!< Offset: 0x030 NHP Pop Register (W) */
__IO uint32_t MODE; /*!< Offset: 0x034 NHP Mode selection Register (W) */
uint32_t RESERVED0[2];
__IO uint32_t HDEN; /*!< Offset: 0x040 Half duplex Enable Register (R/W) */
uint32_t RESERVED1;
__IO uint32_t SCI_CTRL; /*!< Offset: 0x048 Smart card Interface Control Register (R/W) */
__IO uint32_t RS485CTRL; /*!< Offset: 0x04C RS-485/EIA-485 Control Register (R/W) */
__IO uint32_t ADRMATCH; /*!< Offset: 0x050 RS-485/EIA-485 address match Register (R/W) */
__IO uint32_t RS485DLY; /*!< Offset: 0x054 RS-485/EIA-485 direction control delay Register (R/W) */
__IO uint32_t SYNCCTRL; /*!< Offset: 0x058 Synchronous Mode Control Register (R/W ) */
__IO uint32_t TER; /*!< Offset: 0x05C Transmit Enable Register (R/W) */
uint32_t RESERVED2[989];
__I uint32_t CFG; /*!< Offset: 0xFD4 Configuration Register (R) */
__O uint32_t INTCE; /*!< Offset: 0xFD8 Interrupt Clear Enable Register (W) */
__O uint32_t INTSE; /*!< Offset: 0xFDC Interrupt Set Enable Register (W) */
__I uint32_t INTS; /*!< Offset: 0xFE0 Interrupt Status Register (R) */
__I uint32_t INTE; /*!< Offset: 0xFE4 Interrupt Enable Register (R) */
__O uint32_t INTCS; /*!< Offset: 0xFE8 Interrupt Clear Status Register (W) */
__O uint32_t INTSS; /*!< Offset: 0xFEC Interrupt Set Status Register (W) */
uint32_t RESERVED3[3];
__I uint32_t MID; /*!< Offset: 0xFFC Module Identification Register (R) */
} LPC_UART4_TypeDef;
/*------------- Synchronous Serial Communication (SSP) -----------------------*/
typedef struct
{
__IO uint32_t CR0; /*!< Offset: 0x000 Control Register 0 (R/W) */
__IO uint32_t CR1; /*!< Offset: 0x004 Control Register 1 (R/W) */
__IO uint32_t DR; /*!< Offset: 0x008 Data Register (R/W) */
__I uint32_t SR; /*!< Offset: 0x00C Status Registe (R/ ) */
__IO uint32_t CPSR; /*!< Offset: 0x010 Clock Prescale Register (R/W) */
__IO uint32_t IMSC; /*!< Offset: 0x014 Interrupt Mask Set and Clear Register (R/W) */
__IO uint32_t RIS; /*!< Offset: 0x018 Raw Interrupt Status Register (R/W) */
__IO uint32_t MIS; /*!< Offset: 0x01C Masked Interrupt Status Register (R/W) */
__IO uint32_t ICR; /*!< Offset: 0x020 SSPICR Interrupt Clear Register (R/W) */
__IO uint32_t DMACR;
} LPC_SSP_TypeDef;
/*------------- Inter-Integrated Circuit (I2C) -------------------------------*/
typedef struct
{
__IO uint32_t CONSET; /*!< Offset: 0x000 I2C Control Set Register (R/W) */
__I uint32_t STAT; /*!< Offset: 0x004 I2C Status Register (R/ ) */
__IO uint32_t DAT; /*!< Offset: 0x008 I2C Data Register (R/W) */
__IO uint32_t ADR0; /*!< Offset: 0x00C I2C Slave Address Register 0 (R/W) */
__IO uint32_t SCLH; /*!< Offset: 0x010 SCH Duty Cycle Register High Half Word (R/W) */
__IO uint32_t SCLL; /*!< Offset: 0x014 SCL Duty Cycle Register Low Half Word (R/W) */
__O uint32_t CONCLR; /*!< Offset: 0x018 I2C Control Clear Register ( /W) */
__IO uint32_t MMCTRL; /*!< Offset: 0x01C Monitor mode control register (R/W) */
__IO uint32_t ADR1; /*!< Offset: 0x020 I2C Slave Address Register 1 (R/W) */
__IO uint32_t ADR2; /*!< Offset: 0x024 I2C Slave Address Register 2 (R/W) */
__IO uint32_t ADR3; /*!< Offset: 0x028 I2C Slave Address Register 3 (R/W) */
__I uint32_t DATA_BUFFER; /*!< Offset: 0x02C Data buffer register ( /W) */
__IO uint32_t MASK0; /*!< Offset: 0x030 I2C Slave address mask register 0 (R/W) */
__IO uint32_t MASK1; /*!< Offset: 0x034 I2C Slave address mask register 1 (R/W) */
__IO uint32_t MASK2; /*!< Offset: 0x038 I2C Slave address mask register 2 (R/W) */
__IO uint32_t MASK3; /*!< Offset: 0x03C I2C Slave address mask register 3 (R/W) */
} LPC_I2C_TypeDef;
/*------------- Inter IC Sound (I2S) -----------------------------------------*/
typedef struct
{
__IO uint32_t DAO;
__IO uint32_t DAI;
__O uint32_t TXFIFO;
__I uint32_t RXFIFO;
__I uint32_t STATE;
__IO uint32_t DMA1;
__IO uint32_t DMA2;
__IO uint32_t IRQ;
__IO uint32_t TXRATE;
__IO uint32_t RXRATE;
__IO uint32_t TXBITRATE;
__IO uint32_t RXBITRATE;
__IO uint32_t TXMODE;
__IO uint32_t RXMODE;
} LPC_I2S_TypeDef;
/*------------- Real-Time Clock (RTC) ----------------------------------------*/
typedef struct
{
__IO uint8_t ILR;
uint8_t RESERVED0[7];
__IO uint8_t CCR;
uint8_t RESERVED1[3];
__IO uint8_t CIIR;
uint8_t RESERVED2[3];
__IO uint8_t AMR;
uint8_t RESERVED3[3];
__I uint32_t CTIME0;
__I uint32_t CTIME1;
__I uint32_t CTIME2;
__IO uint8_t SEC;
uint8_t RESERVED4[3];
__IO uint8_t MIN;
uint8_t RESERVED5[3];
__IO uint8_t HOUR;
uint8_t RESERVED6[3];
__IO uint8_t DOM;
uint8_t RESERVED7[3];
__IO uint8_t DOW;
uint8_t RESERVED8[3];
__IO uint16_t DOY;
uint16_t RESERVED9;
__IO uint8_t MONTH;
uint8_t RESERVED10[3];
__IO uint16_t YEAR;
uint16_t RESERVED11;
__IO uint32_t CALIBRATION;
__IO uint32_t GPREG0;
__IO uint32_t GPREG1;
__IO uint32_t GPREG2;
__IO uint32_t GPREG3;
__IO uint32_t GPREG4;
__IO uint8_t RTC_AUXEN;
uint8_t RESERVED12[3];
__IO uint8_t RTC_AUX;
uint8_t RESERVED13[3];
__IO uint8_t ALSEC;
uint8_t RESERVED14[3];
__IO uint8_t ALMIN;
uint8_t RESERVED15[3];
__IO uint8_t ALHOUR;
uint8_t RESERVED16[3];
__IO uint8_t ALDOM;
uint8_t RESERVED17[3];
__IO uint8_t ALDOW;
uint8_t RESERVED18[3];
__IO uint16_t ALDOY;
uint16_t RESERVED19;
__IO uint8_t ALMON;
uint8_t RESERVED20[3];
__IO uint16_t ALYEAR;
uint16_t RESERVED21;
__IO uint32_t ERSTATUS;
__IO uint32_t ERCONTROL;
__IO uint32_t ERCOUNTERS;
uint32_t RESERVED22;
__IO uint32_t ERFIRSTSTAMP0;
__IO uint32_t ERFIRSTSTAMP1;
__IO uint32_t ERFIRSTSTAMP2;
uint32_t RESERVED23;
__IO uint32_t ERLASTSTAMP0;
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