📄 lpc177x_8x.h
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/**********************************************************************
* $Id: LPC177x_8x.h 7485 2011-06-03 07:57:16Z sgg06786 $ LPC177x_8x.h 2011-06-02
*//**
* @file LPC177x_8x.h
* @brief Cortex-M3 Core Peripheral Access Layer Header File for
* NXP LPC177x_8x Series.
* @version 1.0
* @date 02. June. 2011
* @author NXP MCU SW Application Team
*
* Copyright(C) 2011, NXP Semiconductor
* All rights reserved.
*
***********************************************************************
* Software that is described herein is for illustrative purposes only
* which provides customers with programming information regarding the
* products. This software is supplied "AS IS" without any warranties.
* NXP Semiconductors assumes no responsibility or liability for the
* use of the software, conveys no license or title under any patent,
* copyright, or mask work right to the product. NXP Semiconductors
* reserves the right to make changes in the software without
* notification. NXP Semiconductors also make no representation or
* warranty that such application will be suitable for the specified
* use without further testing or modification.
**********************************************************************/
#ifndef __LPC177x_8x_H__
#define __LPC177x_8x_H__
/*
* ==========================================================================
* ---------- Interrupt Number Definition -----------------------------------
* ==========================================================================
*/
typedef enum IRQn
{
/****** Cortex-M3 Processor Exceptions Numbers ***************************************************/
NonMaskableInt_IRQn = -14, /*!< 2 Non Maskable Interrupt */
MemoryManagement_IRQn = -12, /*!< 4 Cortex-M3 Memory Management Interrupt */
BusFault_IRQn = -11, /*!< 5 Cortex-M3 Bus Fault Interrupt */
UsageFault_IRQn = -10, /*!< 6 Cortex-M3 Usage Fault Interrupt */
SVCall_IRQn = -5, /*!< 11 Cortex-M3 SV Call Interrupt */
DebugMonitor_IRQn = -4, /*!< 12 Cortex-M3 Debug Monitor Interrupt */
PendSV_IRQn = -2, /*!< 14 Cortex-M3 Pend SV Interrupt */
SysTick_IRQn = -1, /*!< 15 Cortex-M3 System Tick Interrupt */
/****** LPC177x_8x Specific Interrupt Numbers *******************************************************/
WDT_IRQn = 0, /*!< Watchdog Timer Interrupt */
TIMER0_IRQn = 1, /*!< Timer0 Interrupt */
TIMER1_IRQn = 2, /*!< Timer1 Interrupt */
TIMER2_IRQn = 3, /*!< Timer2 Interrupt */
TIMER3_IRQn = 4, /*!< Timer3 Interrupt */
UART0_IRQn = 5, /*!< UART0 Interrupt */
UART1_IRQn = 6, /*!< UART1 Interrupt */
UART2_IRQn = 7, /*!< UART2 Interrupt */
UART3_IRQn = 8, /*!< UART3 Interrupt */
PWM1_IRQn = 9, /*!< PWM1 Interrupt */
I2C0_IRQn = 10, /*!< I2C0 Interrupt */
I2C1_IRQn = 11, /*!< I2C1 Interrupt */
I2C2_IRQn = 12, /*!< I2C2 Interrupt */
Reserved0_IRQn = 13, /*!< Reserved */
SSP0_IRQn = 14, /*!< SSP0 Interrupt */
SSP1_IRQn = 15, /*!< SSP1 Interrupt */
PLL0_IRQn = 16, /*!< PLL0 Lock (Main PLL) Interrupt */
RTC_IRQn = 17, /*!< Real Time Clock Interrupt */
EINT0_IRQn = 18, /*!< External Interrupt 0 Interrupt */
EINT1_IRQn = 19, /*!< External Interrupt 1 Interrupt */
EINT2_IRQn = 20, /*!< External Interrupt 2 Interrupt */
EINT3_IRQn = 21, /*!< External Interrupt 3 Interrupt */
ADC_IRQn = 22, /*!< A/D Converter Interrupt */
BOD_IRQn = 23, /*!< Brown-Out Detect Interrupt */
USB_IRQn = 24, /*!< USB Interrupt */
CAN_IRQn = 25, /*!< CAN Interrupt */
DMA_IRQn = 26, /*!< General Purpose DMA Interrupt */
I2S_IRQn = 27, /*!< I2S Interrupt */
ENET_IRQn = 28, /*!< Ethernet Interrupt */
MCI_IRQn = 29, /*!< SD/MMC card I/F Interrupt */
MCPWM_IRQn = 30, /*!< Motor Control PWM Interrupt */
QEI_IRQn = 31, /*!< Quadrature Encoder Interface Interrupt */
PLL1_IRQn = 32, /*!< PLL1 Lock (USB PLL) Interrupt */
USBActivity_IRQn = 33, /*!< USB Activity interrupt */
CANActivity_IRQn = 34, /*!< CAN Activity interrupt */
UART4_IRQn = 35, /*!< UART4 Interrupt */
SSP2_IRQn = 36, /*!< SSP2 Interrupt */
LCD_IRQn = 37, /*!< LCD Interrupt */
GPIO_IRQn = 38, /*!< GPIO Interrupt */
PWM0_IRQn = 39, /*!< PWM0 Interrupt */
EEPROM_IRQn = 40, /*!< EEPROM Interrupt */
} IRQn_Type;
/*
* ==========================================================================
* ----------- Processor and Core Peripheral Section ------------------------
* ==========================================================================
*/
/* Configuration of the Cortex-M3 Processor and Core Peripherals */
#define __MPU_PRESENT 1 /*!< MPU present or not */
#define __NVIC_PRIO_BITS 5 /*!< Number of Bits used for Priority Levels */
#define __Vendor_SysTickConfig 0 /*!< Set to 1 if different SysTick Config is used */
#include "core_cm3.h" /* Cortex-M3 processor and core peripherals */
//#include "system_LPC177x_8x.h" /* System Header */
/******************************************************************************/
/* Device Specific Peripheral registers structures */
/******************************************************************************/
#if defined ( __CC_ARM )
#pragma anon_unions
#endif
/*------------- System Control (SC) ------------------------------------------*/
typedef struct
{
__IO uint32_t FLASHCFG; /*!< Offset: 0x000 (R/W) Flash Accelerator Configuration Register */
uint32_t RESERVED0[31];
__IO uint32_t PLL0CON; /*!< Offset: 0x080 (R/W) PLL0 Control Register */
__IO uint32_t PLL0CFG; /*!< Offset: 0x084 (R/W) PLL0 Configuration Register */
__I uint32_t PLL0STAT; /*!< Offset: 0x088 (R/ ) PLL0 Status Register */
__O uint32_t PLL0FEED; /*!< Offset: 0x08C ( /W) PLL0 Feed Register */
uint32_t RESERVED1[4];
__IO uint32_t PLL1CON; /*!< Offset: 0x0A0 (R/W) PLL1 Control Register */
__IO uint32_t PLL1CFG; /*!< Offset: 0x0A4 (R/W) PLL1 Configuration Register */
__I uint32_t PLL1STAT; /*!< Offset: 0x0A8 (R/ ) PLL1 Status Register */
__O uint32_t PLL1FEED; /*!< Offset: 0x0AC ( /W) PLL1 Feed Register */
uint32_t RESERVED2[4];
__IO uint32_t PCON; /*!< Offset: 0x0C0 (R/W) Power Control Register */
__IO uint32_t PCONP; /*!< Offset: 0x0C4 (R/W) Power Control for Peripherals Register */
uint32_t RESERVED3[14];
__IO uint32_t EMCCLKSEL; /*!< Offset: 0x100 (R/W) External Memory Controller Clock Selection Register */
__IO uint32_t CCLKSEL; /*!< Offset: 0x104 (R/W) CPU Clock Selection Register */
__IO uint32_t USBCLKSEL; /*!< Offset: 0x108 (R/W) USB Clock Selection Register */
__IO uint32_t CLKSRCSEL; /*!< Offset: 0x10C (R/W) Clock Source Select Register */
__IO uint32_t CANSLEEPCLR; /*!< Offset: 0x110 (R/W) CAN Sleep Clear Register */
__IO uint32_t CANWAKEFLAGS; /*!< Offset: 0x114 (R/W) CAN Wake-up Flags Register */
uint32_t RESERVED4[10];
__IO uint32_t EXTINT; /*!< Offset: 0x140 (R/W) External Interrupt Flag Register */
uint32_t RESERVED5[1];
__IO uint32_t EXTMODE; /*!< Offset: 0x148 (R/W) External Interrupt Mode Register */
__IO uint32_t EXTPOLAR; /*!< Offset: 0x14C (R/W) External Interrupt Polarity Register */
uint32_t RESERVED6[12];
__IO uint32_t RSID; /*!< Offset: 0x180 (R/W) Reset Source Identification Register */
uint32_t RESERVED7[7];
__IO uint32_t SCS; /*!< Offset: 0x1A0 (R/W) System Controls and Status Register */
__IO uint32_t IRCTRIM; /*!< Offset: 0x1A4 (R/W) Clock Dividers */
__IO uint32_t PCLKSEL; /*!< Offset: 0x1A8 (R/W) Peripheral Clock Selection Register */
uint32_t RESERVED8[3];
__IO uint32_t LCD_CFG; /*!< Offset: 0x1B8 (R/W) LCD Configuration and clocking control Register */
uint32_t RESERVED9[1];
__IO uint32_t USBIntSt; /*!< Offset: 0x1C0 (R/W) USB Interrupt Status Register */
__IO uint32_t DMAREQSEL; /*!< Offset: 0x1C4 (R/W) DMA Request Select Register */
__IO uint32_t CLKOUTCFG; /*!< Offset: 0x1C8 (R/W) Clock Output Configuration Register */
__IO uint32_t RSTCON0; /*!< Offset: 0x1CC (R/W) RESET Control0 Register */
__IO uint32_t RSTCON1; /*!< Offset: 0x1D0 (R/W) RESET Control1 Register */
uint32_t RESERVED10[2];
__IO uint32_t EMCDLYCTL; /*!< Offset: 0x1DC (R/W) SDRAM programmable delays */
__IO uint32_t EMCCAL; /*!< Offset: 0x1E0 (R/W) Calibration of programmable delays */
} LPC_SC_TypeDef;
/*------------- Pin Connect Block (PINCON) -----------------------------------*/
typedef struct
{
__IO uint32_t P0_0; /* 0x000 */
__IO uint32_t P0_1;
__IO uint32_t P0_2;
__IO uint32_t P0_3;
__IO uint32_t P0_4;
__IO uint32_t P0_5;
__IO uint32_t P0_6;
__IO uint32_t P0_7;
__IO uint32_t P0_8; /* 0x020 */
__IO uint32_t P0_9;
__IO uint32_t P0_10;
__IO uint32_t P0_11;
__IO uint32_t P0_12;
__IO uint32_t P0_13;
__IO uint32_t P0_14;
__IO uint32_t P0_15;
__IO uint32_t P0_16; /* 0x040 */
__IO uint32_t P0_17;
__IO uint32_t P0_18;
__IO uint32_t P0_19;
__IO uint32_t P0_20;
__IO uint32_t P0_21;
__IO uint32_t P0_22;
__IO uint32_t P0_23;
__IO uint32_t P0_24; /* 0x060 */
__IO uint32_t P0_25;
__IO uint32_t P0_26;
__IO uint32_t P0_27;
__IO uint32_t P0_28;
__IO uint32_t P0_29;
__IO uint32_t P0_30;
__IO uint32_t P0_31;
__IO uint32_t P1_0; /* 0x080 */
__IO uint32_t P1_1;
__IO uint32_t P1_2;
__IO uint32_t P1_3;
__IO uint32_t P1_4;
__IO uint32_t P1_5;
__IO uint32_t P1_6;
__IO uint32_t P1_7;
__IO uint32_t P1_8; /* 0x0A0 */
__IO uint32_t P1_9;
__IO uint32_t P1_10;
__IO uint32_t P1_11;
__IO uint32_t P1_12;
__IO uint32_t P1_13;
__IO uint32_t P1_14;
__IO uint32_t P1_15;
__IO uint32_t P1_16; /* 0x0C0 */
__IO uint32_t P1_17;
__IO uint32_t P1_18;
__IO uint32_t P1_19;
__IO uint32_t P1_20;
__IO uint32_t P1_21;
__IO uint32_t P1_22;
__IO uint32_t P1_23;
__IO uint32_t P1_24; /* 0x0E0 */
__IO uint32_t P1_25;
__IO uint32_t P1_26;
__IO uint32_t P1_27;
__IO uint32_t P1_28;
__IO uint32_t P1_29;
__IO uint32_t P1_30;
__IO uint32_t P1_31;
__IO uint32_t P2_0; /* 0x100 */
__IO uint32_t P2_1;
__IO uint32_t P2_2;
__IO uint32_t P2_3;
__IO uint32_t P2_4;
__IO uint32_t P2_5;
__IO uint32_t P2_6;
__IO uint32_t P2_7;
__IO uint32_t P2_8; /* 0x120 */
__IO uint32_t P2_9;
__IO uint32_t P2_10;
__IO uint32_t P2_11;
__IO uint32_t P2_12;
__IO uint32_t P2_13;
__IO uint32_t P2_14;
__IO uint32_t P2_15;
__IO uint32_t P2_16; /* 0x140 */
__IO uint32_t P2_17;
__IO uint32_t P2_18;
__IO uint32_t P2_19;
__IO uint32_t P2_20;
__IO uint32_t P2_21;
__IO uint32_t P2_22;
__IO uint32_t P2_23;
__IO uint32_t P2_24; /* 0x160 */
__IO uint32_t P2_25;
__IO uint32_t P2_26;
__IO uint32_t P2_27;
__IO uint32_t P2_28;
__IO uint32_t P2_29;
__IO uint32_t P2_30;
__IO uint32_t P2_31;
__IO uint32_t P3_0; /* 0x180 */
__IO uint32_t P3_1;
__IO uint32_t P3_2;
__IO uint32_t P3_3;
__IO uint32_t P3_4;
__IO uint32_t P3_5;
__IO uint32_t P3_6;
__IO uint32_t P3_7;
__IO uint32_t P3_8; /* 0x1A0 */
__IO uint32_t P3_9;
__IO uint32_t P3_10;
__IO uint32_t P3_11;
__IO uint32_t P3_12;
__IO uint32_t P3_13;
__IO uint32_t P3_14;
__IO uint32_t P3_15;
__IO uint32_t P3_16; /* 0x1C0 */
__IO uint32_t P3_17;
__IO uint32_t P3_18;
__IO uint32_t P3_19;
__IO uint32_t P3_20;
__IO uint32_t P3_21;
__IO uint32_t P3_22;
__IO uint32_t P3_23;
__IO uint32_t P3_24; /* 0x1E0 */
__IO uint32_t P3_25;
__IO uint32_t P3_26;
__IO uint32_t P3_27;
__IO uint32_t P3_28;
__IO uint32_t P3_29;
__IO uint32_t P3_30;
__IO uint32_t P3_31;
__IO uint32_t P4_0; /* 0x200 */
__IO uint32_t P4_1;
__IO uint32_t P4_2;
__IO uint32_t P4_3;
__IO uint32_t P4_4;
__IO uint32_t P4_5;
__IO uint32_t P4_6;
__IO uint32_t P4_7;
__IO uint32_t P4_8; /* 0x220 */
__IO uint32_t P4_9;
__IO uint32_t P4_10;
__IO uint32_t P4_11;
__IO uint32_t P4_12;
__IO uint32_t P4_13;
__IO uint32_t P4_14;
__IO uint32_t P4_15;
__IO uint32_t P4_16; /* 0x240 */
__IO uint32_t P4_17;
__IO uint32_t P4_18;
__IO uint32_t P4_19;
__IO uint32_t P4_20;
__IO uint32_t P4_21;
__IO uint32_t P4_22;
__IO uint32_t P4_23;
__IO uint32_t P4_24; /* 0x260 */
__IO uint32_t P4_25;
__IO uint32_t P4_26;
__IO uint32_t P4_27;
__IO uint32_t P4_28;
__IO uint32_t P4_29;
__IO uint32_t P4_30;
__IO uint32_t P4_31;
__IO uint32_t P5_0; /* 0x280 */
__IO uint32_t P5_1;
__IO uint32_t P5_2;
__IO uint32_t P5_3;
__IO uint32_t P5_4; /* 0x290 */
} LPC_IOCON_TypeDef;
/*------------- General Purpose Input/Output (GPIO) --------------------------*/
typedef struct
{
__IO uint32_t DIR;
uint32_t RESERVED0[3];
__IO uint32_t MASK;
__IO uint32_t PIN;
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