📄 sys.lst
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298 //Setting Port 9 direction register
299 PD9 = 0xFF; // XXXX XXXX
\ 000047 74CFF303 MOV.B #255,1011
\ FF
300 // |||| |||+- Port P90 direction register
301 // |||| ||| 0: Input mode
302 // |||| ||| 1: Output mode
303 // |||| ||+-- Port P91 direction register
304 // |||| || 0: Input mode
305 // |||| || 1: Output mode
306 // |||| |+--- Port P92 direction register
307 // |||| | 0: Input mode
308 // |||| | 1: Output mode
309 // |||| +---- Port P93 direction register
310 // |||| 0: Input mode
311 // |||| 1: Output mode
312 // |||+------ Port P94 direction register
313 // ||| 0: Input mode
314 // ||| 1: Output mode
315 // ||+------- Port P95 direction register
316 // || 0: Input mode
317 // || 1: Output mode
318 // |+-------- Port P96 direction register
319 // | 0: Input mode
320 // | 1: Output mode
321 // +--------- Port P97 direction register
322 // 0: Input mode
323 // 1: Output mode
324
325 // Writing inhibited
326 protection_set_port9 ();
\ 00004C F5C7FF JSR.W protection_set_port9
327 }
\ 00004F ED01 POPM R0
\ 000051 F3 RTS
\ system_clock_low_power:
328
329 /**************************************************************************/
330 /* */
331 /* System clock - Low Power-Initialization */
332 /* */
333 /* Name : system_clock_low_power */
334 /* Date/Author : 05.05.1997/GA */
335 /* Parameter : */
336 /* Return : */
337 /* */
338 /**************************************************************************/
339 void near system_clock_low_power (void)
340 {
\ 000052 EC80 PUSHM R0
341 // Writing enablen
342 protection_clr_system_clock ();
\ 000054 F5B0FF JSR.W protection_clr_system_clock
343
344 //Setting System clock control register 0
345 CM0 &= ~0x08; // ---- 0---
\ 000057 97F70600 AND.B #247,6
346 // +---- Xcin-Xcout drive capacity select bit
347 // 0: LOW
348 // 1: HIGH
349
350 //Setting System clock control register 1
351 CM1 &= ~0x20; // --00 000-
\ 00005B 97DF0700 AND.B #223,7
352 // |||| ||+-- Always set to '0'
353 // |||| |+--- Always set to '0'
354 // |||| +---- Always set to '0'
355 // |||+------ Always set to '0'
356 // ||+------- Xin-Xout drive capacity select bit
357 // 0: LOW
358 // 1: HIGH
359
360 // Writing inhibited
361 protection_set_system_clock ();
\ 00005F F5A0FF JSR.W protection_set_system_clock
362 }
\ 000062 ED01 POPM R0
\ 000064 F3 RTS
\ watchdog:
363
364 /**************************************************************************/
365 /* */
366 /* WATCHDOG-TIMER - Initialization */
367 /* */
368 /* Name : watchdog */
369 /* Date/Author : 06.05.1997/GA */
370 /* Parameter : */
371 /* Return : */
372 /* */
373 /**************************************************************************/
374 void near watchdog (void)
375 {
376 //Setting Watchdog timer control register
377 WDC = 0x08; // X00X XXXX
\ 000065 74CF0F00 MOV.B #8,15
\ 08
378 // |||| |||+- Bit 8 of watchdog timer
379 // |||| ||+-- Bit 9 of watchdog timer
380 // |||| |+--- Bit 10 of watchdog timer
381 // |||| +---- Bit 11 of watchdog timer
382 // |||+------ Bit 12 of watchdog timer
383 // ||+------- Must always be set to '0'
384 // |+-------- Must always be set to '0'
385 // +--------- Prescaler select bit
386 // 0: Divided by 16
387 // 1: Divided by 128
388 }
\ 00006A F3 RTS
\ software_reset:
389
390 /**************************************************************************/
391 /* */
392 /* Software reset */
393 /* */
394 /* Name : software_reset */
395 /* Date/Author : 06.05.1997/GA */
396 /* Parameter : */
397 /* Return : */
398 /* */
399 /**************************************************************************/
400 void near software_reset (void)
401 {
\ 00006B EC80 PUSHM R0
402 // Writing enablen
403 protection_clr_processor_mode ();
\ 00006D F5A1FF JSR.W protection_clr_processor_mode
404
405 //Setting Processor mode register 0
406 PM0 |= 0x08; // ---- 1---
\ 000070 9F080400 OR.B #8,4
407 // |||| +---- Software reset bit
408 // |||| The device is reset when this
409 // |||| bit is set to '1'.
410 }
\ 000074 ED01 POPM R0
\ 000076 F3 RTS
\ stop_mode:
411
412 /**************************************************************************/
413 /* */
414 /* Stop mode */
415 /* */
416 /* Name : stop_mode */
417 /* Date/Author : 05.05.1997/GA */
418 /* Parameter : */
419 /* Return : */
420 /* */
421 /**************************************************************************/
422 void near stop_mode (void)
423 {
\ 000077 EC80 PUSHM R0
424 // Writing enablen
425 protection_clr_system_clock ();
\ 000079 F58BFF JSR.W protection_clr_system_clock
426
427 //Setting System clock control register 1
428 CM1 |= 0x01; // ---0 0001
\ 00007C 9F010700 OR.B #1,7
429 // | |||+- All clock stop control bit
430 // | ||| 0: Clock on
431 // | ||| 1: All Clock off (stop mode)
432 // | ||+-- Always set to '0'
433 // | |+--- Always set to '0'
434 // | +---- Always set to '0'
435 // +------ Always set to '0'
436
437 // Writing inhibited
438 protection_set_system_clock ();
\ 000080 F57FFF JSR.W protection_set_system_clock
439 }
\ 000083 ED01 POPM R0
\ 000085 F3 RTS
440
441
\ END
Errors: none
Warnings: none
Code size: 134
Constant size: 0
Static variable size: 0
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