📄 sys.lst
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138 PRCR &= ~0x04; // ---- -0--
\ 000014 97FB0A00 AND.B #251,10
139 // +--- Inhibite write to Port9 direction
140 // register
141 // 0: Write inhibited
142 // 1: Write enabled
143 }
\ 000018 F3 RTS
\ protection_clr_port9:
144
145 /**************************************************************************/
146 /* */
147 /* Protection - Port9 direction register write enable */
148 /* */
149 /* Name : protection_clr_system_clock */
150 /* Date/Author : 02.05.1997/GA */
151 /* Parameter : */
152 /* Return : */
153 /* */
154 /**************************************************************************/
155 void near protection_clr_port9 (void)
156 {
157 PRCR |= 0x04; // ---- -1--
\ 000019 9F040A00 OR.B #4,10
158 // +--- Enable write to Port9 direction
159 // register
160 // 0: Write inhibited
161 // 1: Write enabled
162 }
\ 00001D F3 RTS
\ processor_mode_set:
163
164 /**************************************************************************/
165 /* */
166 /* Processor mode - Initialization */
167 /* */
168 /* Name : processor_mode_set */
169 /* Date/Author : 29.04.1997/GA */
170 /* Parameter : */
171 /* Return : */
172 /* */
173 /**************************************************************************/
174 void near processor_mode_set (void)
175 {
\ 00001E EC80 PUSHM R0
176 // Writing enablen
177 protection_clr_processor_mode ();
\ 000020 F5EEFF JSR.W protection_clr_processor_mode
178
179 //Setting Processor mode register 0
180 PM0 = 0xC0; // XXXX XXXX
\ 000023 74CF0400 MOV.B #192,4
\ C0
181 // |||| |||+- Processor mode bit
182 // |||| ||+-- Processor mode bit
183 // |||| || 00: Single-chip mode
184 // |||| || 01: Memory expansion mode
185 // |||| || 10: Inhibited
186 // |||| || 11: Microprocessor mode
187 // |||| |+--- R/W mode select bit
188 // |||| | 0: /RD, /BHE, /WR
189 // |||| | 1: /RD, /WRH, /WRL
190 // |||| +---- Software reset bit
191 // |||| The device is reset when this
192 // |||| bit is set to '1'.
193 // |||+------ Multiplexed bus space select bit
194 // ||+------- Multiplexed bus space select bit
195 // || 00: Multiplexed bus is not used
196 // || 01: Allocated to CS2 space
197 // || 10: Allocated to CS1 space
198 // || 11: Allocated to entire space
199 // |+-------- Port P40 to P43 function select bit
200 // | 0: Address output
201 // | 1: Port function (Address is no output)
202 // +----------BCLK output disable bit
203 // 0: BCLK is output
204 // 1: BCLK is not output
205
206 //Setting Processor mode register 1
207 PM1 = 0x00; // X--- ---0
\ 000028 B70500 MOV.B #0,5
208 // | +- Must always be set to '0'
209 // +--------- Wait bit
210 // 0: No wait state
211 // 1: Wait state inserted
212
213 // Writing inhibited
214 protection_set_processor_mode ();
\ 00002B F5DEFF JSR.W protection_set_processor_mode
215 }
\ 00002E ED01 POPM R0
\ 000030 F3 RTS
\ system_clock_set:
216
217 /**************************************************************************/
218 /* */
219 /* System clock - Initialization */
220 /* */
221 /* Name : system_clock_set */
222 /* Date/Author : 05.05.1997/GA */
223 /* Parameter : */
224 /* Return : */
225 /* */
226 /**************************************************************************/
227 void near system_clock_set (void)
228 {
\ 000031 EC80 PUSHM R0
229 // Writing enablen
230 protection_clr_system_clock ();
\ 000033 F5D1FF JSR.W protection_clr_system_clock
231
232 //Setting System clock control register 0
233 CM0 = 0x00; // XXXX XXXX
\ 000036 B70600 MOV.B #0,6
234 // |||| |||+- Clock output function select bit
235 // |||| ||+-- Clock output function select bit
236 // |||| || 00: I/O port P57
237 // |||| || 01: fc output
238 // |||| || 10: f8 output
239 // |||| || 11: f32 output
240 // |||| |+--- WAIT peripheral function clock stop bit
241 // |||| | 0: Do not stop f1, f8, f32 in
242 // |||| | wait mode
243 // |||| | 1: Stop f1, f8, f32 in wait mode
244 // |||| +---- Xcin-Xcout drive capacity select bit
245 // |||| 0: LOW
246 // |||| 1: HIGH
247 // |||+------ Port Xc select bit
248 // ||| 0: I/O port
249 // ||| 1: Xcin-Xcout generation
250 // ||+------- Main clock (Xin-Xout) stop bit
251 // || 0: On
252 // || 1: Off
253 // |+-------- Main clock division select bit 0
254 // | 0: CM16 and cM17 valid
255 // | 1: Division by 8 mode
256 // +--------- System clock select bit
257 // 0: Xin-Xout
258 // 1: Xcin-Xcout
259
260 //Setting System clock control register 1
261 CM1 = 0x00; // XXX0 000X
\ 000039 B70700 MOV.B #0,7
262 // |||| |||+- All clock stop control bit
263 // |||| ||| 0: Clock on
264 // |||| ||| 1: All Clock off (stop mode)
265 // |||| ||+-- Always set to '0'
266 // |||| |+--- Always set to '0'
267 // |||| +---- Always set to '0'
268 // |||+------ Always set to '0'
269 // ||+------- Xin-Xout drive capacity select bit
270 // || 0: LOW
271 // || 1: HIGH
272 // |+-------- Main clock division mode
273 // +--------- Main clock division mode
274 // 00: No division mode
275 // 01: Division by 2 mode
276 // 10: Division by 4 mode
277 // 11: Division by 16 mode
278
279 // Writing inhibited
280 protection_set_system_clock ();
\ 00003C F5C3FF JSR.W protection_set_system_clock
281 }
\ 00003F ED01 POPM R0
\ 000041 F3 RTS
\ port9_set:
282
283 /**************************************************************************/
284 /* */
285 /* Port 9 direction-Initialization */
286 /* */
287 /* Name : port9_set */
288 /* Date/Author : 05.05.1997/GA */
289 /* Parameter : */
290 /* Return : */
291 /* */
292 /**************************************************************************/
293 void near port9_set (void)
294 {
\ 000042 EC80 PUSHM R0
295 // Writing enablen
296 protection_clr_port9 ();
\ 000044 F5D4FF JSR.W protection_clr_port9
297
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