📄 sys.c
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/* Date/Author : 05.05.1997/GA */
/* Parameter : */
/* Return : */
/* */
/**************************************************************************/
void near system_clock_set (void)
{
// Writing enablen
protection_clr_system_clock ();
//Setting System clock control register 0
CM0 = 0x00; // XXXX XXXX
// |||| |||+- Clock output function select bit
// |||| ||+-- Clock output function select bit
// |||| || 00: I/O port P57
// |||| || 01: fc output
// |||| || 10: f8 output
// |||| || 11: f32 output
// |||| |+--- WAIT peripheral function clock stop bit
// |||| | 0: Do not stop f1, f8, f32 in
// |||| | wait mode
// |||| | 1: Stop f1, f8, f32 in wait mode
// |||| +---- Xcin-Xcout drive capacity select bit
// |||| 0: LOW
// |||| 1: HIGH
// |||+------ Port Xc select bit
// ||| 0: I/O port
// ||| 1: Xcin-Xcout generation
// ||+------- Main clock (Xin-Xout) stop bit
// || 0: On
// || 1: Off
// |+-------- Main clock division select bit 0
// | 0: CM16 and cM17 valid
// | 1: Division by 8 mode
// +--------- System clock select bit
// 0: Xin-Xout
// 1: Xcin-Xcout
//Setting System clock control register 1
CM1 = 0x00; // XXX0 000X
// |||| |||+- All clock stop control bit
// |||| ||| 0: Clock on
// |||| ||| 1: All Clock off (stop mode)
// |||| ||+-- Always set to '0'
// |||| |+--- Always set to '0'
// |||| +---- Always set to '0'
// |||+------ Always set to '0'
// ||+------- Xin-Xout drive capacity select bit
// || 0: LOW
// || 1: HIGH
// |+-------- Main clock division mode
// +--------- Main clock division mode
// 00: No division mode
// 01: Division by 2 mode
// 10: Division by 4 mode
// 11: Division by 16 mode
// Writing inhibited
protection_set_system_clock ();
}
/**************************************************************************/
/* */
/* Port 9 direction-Initialization */
/* */
/* Name : port9_set */
/* Date/Author : 05.05.1997/GA */
/* Parameter : */
/* Return : */
/* */
/**************************************************************************/
void near port9_set (void)
{
// Writing enablen
protection_clr_port9 ();
//Setting Port 9 direction register
PD9 = 0xFF; // XXXX XXXX
// |||| |||+- Port P90 direction register
// |||| ||| 0: Input mode
// |||| ||| 1: Output mode
// |||| ||+-- Port P91 direction register
// |||| || 0: Input mode
// |||| || 1: Output mode
// |||| |+--- Port P92 direction register
// |||| | 0: Input mode
// |||| | 1: Output mode
// |||| +---- Port P93 direction register
// |||| 0: Input mode
// |||| 1: Output mode
// |||+------ Port P94 direction register
// ||| 0: Input mode
// ||| 1: Output mode
// ||+------- Port P95 direction register
// || 0: Input mode
// || 1: Output mode
// |+-------- Port P96 direction register
// | 0: Input mode
// | 1: Output mode
// +--------- Port P97 direction register
// 0: Input mode
// 1: Output mode
// Writing inhibited
protection_set_port9 ();
}
/**************************************************************************/
/* */
/* System clock - Low Power-Initialization */
/* */
/* Name : system_clock_low_power */
/* Date/Author : 05.05.1997/GA */
/* Parameter : */
/* Return : */
/* */
/**************************************************************************/
void near system_clock_low_power (void)
{
// Writing enablen
protection_clr_system_clock ();
//Setting System clock control register 0
CM0 &= ~0x08; // ---- 0---
// +---- Xcin-Xcout drive capacity select bit
// 0: LOW
// 1: HIGH
//Setting System clock control register 1
CM1 &= ~0x20; // --00 000-
// |||| ||+-- Always set to '0'
// |||| |+--- Always set to '0'
// |||| +---- Always set to '0'
// |||+------ Always set to '0'
// ||+------- Xin-Xout drive capacity select bit
// 0: LOW
// 1: HIGH
// Writing inhibited
protection_set_system_clock ();
}
/**************************************************************************/
/* */
/* WATCHDOG-TIMER - Initialization */
/* */
/* Name : watchdog */
/* Date/Author : 06.05.1997/GA */
/* Parameter : */
/* Return : */
/* */
/**************************************************************************/
void near watchdog (void)
{
//Setting Watchdog timer control register
WDC = 0x08; // X00X XXXX
// |||| |||+- Bit 8 of watchdog timer
// |||| ||+-- Bit 9 of watchdog timer
// |||| |+--- Bit 10 of watchdog timer
// |||| +---- Bit 11 of watchdog timer
// |||+------ Bit 12 of watchdog timer
// ||+------- Must always be set to '0'
// |+-------- Must always be set to '0'
// +--------- Prescaler select bit
// 0: Divided by 16
// 1: Divided by 128
}
/**************************************************************************/
/* */
/* Software reset */
/* */
/* Name : software_reset */
/* Date/Author : 06.05.1997/GA */
/* Parameter : */
/* Return : */
/* */
/**************************************************************************/
void near software_reset (void)
{
// Writing enablen
protection_clr_processor_mode ();
//Setting Processor mode register 0
PM0 |= 0x08; // ---- 1---
// |||| +---- Software reset bit
// |||| The device is reset when this
// |||| bit is set to '1'.
}
/**************************************************************************/
/* */
/* Stop mode */
/* */
/* Name : stop_mode */
/* Date/Author : 05.05.1997/GA */
/* Parameter : */
/* Return : */
/* */
/**************************************************************************/
void near stop_mode (void)
{
// Writing enablen
protection_clr_system_clock ();
//Setting System clock control register 1
CM1 |= 0x01; // ---0 0001
// | |||+- All clock stop control bit
// | ||| 0: Clock on
// | ||| 1: All Clock off (stop mode)
// | ||+-- Always set to '0'
// | |+--- Always set to '0'
// | +---- Always set to '0'
// +------ Always set to '0'
// Writing inhibited
protection_set_system_clock ();
}
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