sys.c

瑞萨单片机LCD控制

/**************************************************************************/
/**MITSUBISHI**MITSUBISHI**MITSUBISHI**MITSUBISHI**MITSUBISHI**MITSUBISHI**/
/**************************************************************************/
/**************************************************************************/
/*  DISCLAIMER:                                                           */
/*  We (MITSUBISHI ELECTRIC B.V.) do not warrant that the Software is     */
/*  free from claims by a third party of copyright, patent, trademark,    */
/*  trade secret or any other intellectual property infringement.         */
/*                                                                        */
/*  Under no circumstances are we liable for any of the following:        */
/*                                                                        */
/*  1. third-party claims against you for losses or damages;              */
/*  2. loss of, or damage to, your records or data; or                    */
/*  3. economic consequential damages (including lost profits or          */
/*     savings) or incidental damages, even if we are informed of         */
/*     their possibility.                                                 */
/*                                                                        */
/*  We do not warrant uninterrupted or error free operation of the        */
/*  Software. We have no obligation to provide service, defect            */
/*  correction, or any maintenance for the Software. We have no           */
/*  obligation to supply any Software updates or enhancements to you      */
/*  even if such are or later become available.                           */
/*                                                                        */
/*  IF YOU DOWNLOAD OR USE THIS SOFTWARE YOU AGREE TO THESE TERMS.        */
/*                                                                        */
/*  THERE ARE NO WARRANTIES, EXPRESS OR IMPLIED, INCLUDING THE            */
/*  IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A               */
/*  PARTICULAR PURPOSE.                                                   */
/**************************************************************************/
/**************************************************************************/
/*                                                                        */
/*       System Initialization and Service-Routines for the M3060         */
/*                                                                        */
/*       Name         :      SYS.C                                        */
/*       Date/Author  :      29.04.1997/GA                                */
/*       Change       :                                                   */
/*               (Date)  (Author)  (Description)                          */
/*                                                                        */
/**************************************************************************/

#define public extern
#include    "sfr_3061.h"
#undef public

#define public 
#include    "sys.h"
#undef public


/**************************************************************************/
/*                                                                        */
/*       Protection - system clock control register write inhibite        */
/*                                                                        */
/*       Name         :     protection_set_system_clock                   */
/*       Date/Author  :     02.05.1997/GA                                 */
/*       Parameter    :                                                   */
/*       Return       :                                                   */
/*                                                                        */
/**************************************************************************/
void near protection_set_system_clock (void)
{   
    PRCR &= ~0x01;          // ---- ---0
                            //         +- Inhibite write to system clock
                            //            control registers 0 and 1    
                            //            0: Write inhibited
                            //            1: Write enabled
}

/**************************************************************************/
/*                                                                        */
/*       Protection - system clock control register write enable          */
/*                                                                        */
/*       Name         :     protection_clr_system_clock                   */
/*       Date/Author  :     02.05.1997/GA                                 */
/*       Parameter    :                                                   */
/*       Return       :                                                   */
/*                                                                        */
/**************************************************************************/
void near protection_clr_system_clock (void)
{   
    PRCR |= 0x01;           // ---- ---1
                            //         +- Enable write to system clock
                            //            control registers 0 and 1    
                            //            0: Write inhibited
                            //            1: Write enabled
}

/**************************************************************************/
/*                                                                        */
/*       Protection - processor mode register write inhibite              */
/*                                                                        */
/*       Name         :     protection_set_processor_mode                 */
/*       Date/Author  :     29.04.1997/GA                                 */
/*       Parameter    :                                                   */
/*       Return       :                                                   */
/*                                                                        */
/**************************************************************************/
void near protection_set_processor_mode (void)
{   
    PRCR &= ~0x02;          // ---- --0-
                            //        +-- Inhibite write to processor mode
                            //            registers 0 and 1    
                            //            0: Write inhibited
                            //            1: Write enabled
}

/**************************************************************************/
/*                                                                        */
/*       Protection - system clock control register write enable          */
/*                                                                        */
/*       Name         :     protection_clr_processor_mode                 */
/*       Date/Author  :     29.04.1997/GA                                 */
/*       Parameter    :                                                   */
/*       Return       :                                                   */
/*                                                                        */
/**************************************************************************/
void near protection_clr_processor_mode (void)
{   
    PRCR |= 0x02;           // ---- --1-
                            //        +-- Enable write to processor mode     
                            //            registers 0 and 1    
                            //            0: Write inhibited
                            //            1: Write enabled
}

/**************************************************************************/
/*                                                                        */
/*       Protection - Port9 direction register write inhibite             */
/*                                                                        */
/*       Name         :     protection_set_system_clock                   */
/*       Date/Author  :     02.05.1997/GA                                 */
/*       Parameter    :                                                   */
/*       Return       :                                                   */
/*                                                                        */
/**************************************************************************/
void near protection_set_port9 (void)
{   
    PRCR &= ~0x04;          // ---- -0--
                            //       +--- Inhibite write to Port9 direction 
                            //            register    
                            //            0: Write inhibited
                            //            1: Write enabled
}

/**************************************************************************/
/*                                                                        */
/*       Protection - Port9 direction register write enable               */
/*                                                                        */
/*       Name         :     protection_clr_system_clock                   */
/*       Date/Author  :     02.05.1997/GA                                 */
/*       Parameter    :                                                   */
/*       Return       :                                                   */
/*                                                                        */
/**************************************************************************/
void near protection_clr_port9 (void)
{   
    PRCR |= 0x04;           // ---- -1--
                            //       +--- Enable write to Port9 direction 
                            //            register    
                            //            0: Write inhibited
                            //            1: Write enabled
}

/**************************************************************************/
/*                                                                        */
/*       Processor mode - Initialization                                  */
/*                                                                        */
/*       Name         :     processor_mode_set                            */
/*       Date/Author  :     29.04.1997/GA                                 */
/*       Parameter    :                                                   */
/*       Return       :                                                   */
/*                                                                        */
/**************************************************************************/
void near processor_mode_set (void)
{   
    // Writing enablen 
    protection_clr_processor_mode ();

    //Setting Processor mode register 0
    PM0 = 0xC0;             // XXXX XXXX
                            // |||| |||+- Processor mode bit
                            // |||| ||+-- Processor mode bit
                            // |||| ||    00: Single-chip mode
                            // |||| ||    01: Memory expansion mode
                            // |||| ||    10: Inhibited
                            // |||| ||    11: Microprocessor mode
                            // |||| |+--- R/W mode select bit
                            // |||| |     0: /RD, /BHE, /WR
                            // |||| |     1: /RD, /WRH, /WRL
                            // |||| +---- Software reset bit
                            // ||||       The device is reset when this
                            // ||||       bit is set to '1'.
                            // |||+------ Multiplexed bus space select bit
                            // ||+------- Multiplexed bus space select bit
                            // ||         00: Multiplexed bus is not used
                            // ||         01: Allocated to CS2 space
                            // ||         10: Allocated to CS1 space
                            // ||         11: Allocated to entire space
                            // |+-------- Port P40 to P43 function select bit
                            // |          0: Address output
                            // |          1: Port function (Address is no output)
                            // +----------BCLK output disable bit
                            //            0: BCLK is output
                            //            1: BCLK is not output

    //Setting Processor mode register 1
    PM1 = 0x00;             // X--- ---0
                            // |       +- Must always be set to '0'
                            // +--------- Wait bit
                            //            0: No wait state
                            //            1: Wait state inserted

    // Writing inhibited
    protection_set_processor_mode ();
}

/**************************************************************************/
/*                                                                        */
/*       System clock - Initialization                                    */
/*                                                                        */
/*       Name         :     system_clock_set                              */