📄 davincievm.h
字号:
/*
* Copyright 2005 by Spectrum Digital Incorporated.
* All rights reserved. Property of Spectrum Digital Incorporated.
*
* Not for distribution.
*/
/*
* Definitions & Register for DaVinci EVM
*
*/
/* ------------------------------------------------------------------------ *
* *
* Variable types *
* *
* ------------------------------------------------------------------------ */
#define Uint32 unsigned int
#define Uint16 unsigned short
#define Uint8 unsigned char
#define Int32 int
#define Int16 short
#define Int8 char
/* ------------------------------------------------------------------------ *
* *
* Software Breakpoint code *
* Uses inline assembly command *
* *
* ------------------------------------------------------------------------ */
#ifdef ARM_SIDE
#define SW_BREAKPOINT asm( " .long 0xE1200070" );
#elif DSP_SIDE
#define SW_BREAKPOINT asm( " .long 0x1001E000" );
#endif
/* ------------------------------------------------------------------------ *
* *
* PLL1 Controller *
* Generates DSP, ARM clocks *
* *
* ------------------------------------------------------------------------ */
#define PLL1_BASE 0x01C40800
#define PLL1_PLLCTL *( volatile Uint32* )( PLL1_BASE + 0x100 ) // PLL Control Register
#define PLL1_OCSEL *( volatile Uint32* )( PLL1_BASE + 0x104 ) // OBSCLK Select Register
#define PLL1_SECCTL *( volatile Uint32* )( PLL1_BASE + 0x108 ) // PLL Secondary Control Register
#define PLL1_PLLM *( volatile Uint32* )( PLL1_BASE + 0x110 ) // PLL Multiplier Control Register
#define PLL1_PREDIV *( volatile Uint32* )( PLL1_BASE + 0x114 ) // PLL Pre-Divider control Register
#define PLL1_PLLDIV1 *( volatile Uint32* )( PLL1_BASE + 0x118 ) // PLL Controller Div1 Register
#define PLL1_PLLDIV2 *( volatile Uint32* )( PLL1_BASE + 0x11C ) // PLL Controller Div2 Register
#define PLL1_PLLDIV3 *( volatile Uint32* )( PLL1_BASE + 0x120 ) // PLL Controller Div3 Register
#define PLL1_OSCDIV1 *( volatile Uint32* )( PLL1_BASE + 0x124 ) // Oscilator Divider Register
#define PLL1_POSTDIV *( volatile Uint32* )( PLL1_BASE + 0x128 ) // PLL Post-Divider Register
#define PLL1_BPDIV *( volatile Uint32* )( PLL1_BASE + 0x12C ) // Bypass Divider Register
#define PLL1_WAKEUP *( volatile Uint32* )( PLL1_BASE + 0x130 ) // Wakeup Register
#define PLL1_PLLCMD *( volatile Uint32* )( PLL1_BASE + 0x138 ) // PLL Controller Command Register
#define PLL1_PLLSTAT *( volatile Uint32* )( PLL1_BASE + 0x13C ) // PLL Controller Status Register
#define PLL1_ALNCTL *( volatile Uint32* )( PLL1_BASE + 0x140 ) // PLL Controller Clock Align Control Register
#define PLL1_DCHANGE *( volatile Uint32* )( PLL1_BASE + 0x144 ) // PLLDiv Ratio Change status Register
#define PLL1_CKEN *( volatile Uint32* )( PLL1_BASE + 0x148 ) // Clock Enable Control Register
#define PLL1_CKSTAT *( volatile Uint32* )( PLL1_BASE + 0x14C ) // Clock Status Register
#define PLL1_SYSTAT *( volatile Uint32* )( PLL1_BASE + 0x150 ) // SYSCLK Status Register
#define PLL1_PLLDIV4 *( volatile Uint32* )( PLL1_BASE + 0x160 ) // PLL Controller Div4 Register
#define PLL1_PLLDIV5 *( volatile Uint32* )( PLL1_BASE + 0x164 ) // PLL Controller Div5 Register
#define PLL1_PLLDIV6 *( volatile Uint32* )( PLL1_BASE + 0x168 ) // PLL Controller Div6 Register
#define PLL1_PLLDIV7 *( volatile Uint32* )( PLL1_BASE + 0x16C ) // PLL Controller Div7 Register
#define PLL1_PLLDIV8 *( volatile Uint32* )( PLL1_BASE + 0x170 ) // PLL Controller Div8 Register
/* ------------------------------------------------------------------------ *
* *
* PLL1 Controller *
* Generates DDR2, VPBE clocks *
* *
* ------------------------------------------------------------------------ */
#define PLL2_BASE 0x01C40C00
#define PLL2_PLLCTL *( volatile Uint32* )( PLL2_BASE + 0x100 ) // PLL Control Register
#define PLL2_OCSEL *( volatile Uint32* )( PLL2_BASE + 0x104 ) // OBSCLK Select Register
#define PLL2_SECCTL *( volatile Uint32* )( PLL2_BASE + 0x108 ) // PLL Secondary Control Register
#define PLL2_PLLM *( volatile Uint32* )( PLL2_BASE + 0x110 ) // PLL Multiplier Control Register
#define PLL2_PREDIV *( volatile Uint32* )( PLL2_BASE + 0x114 ) // PLL Pre-Divider control Register
#define PLL2_PLLDIV1 *( volatile Uint32* )( PLL2_BASE + 0x118 ) // PLL Controller Div1 Register
#define PLL2_PLLDIV2 *( volatile Uint32* )( PLL2_BASE + 0x11C ) // PLL Controller Div2 Register
#define PLL2_PLLDIV3 *( volatile Uint32* )( PLL2_BASE + 0x120 ) // PLL Controller Div3 Register
#define PLL2_OSCDIV1 *( volatile Uint32* )( PLL2_BASE + 0x124 ) // Oscilator Divider Register
#define PLL2_POSTDIV *( volatile Uint32* )( PLL2_BASE + 0x128 ) // PLL Post-Divider Register
#define PLL2_BPDIV *( volatile Uint32* )( PLL2_BASE + 0x12C ) // Bypass Divider Register
#define PLL2_WAKEUP *( volatile Uint32* )( PLL2_BASE + 0x130 ) // Wakeup Register
#define PLL2_PLLCMD *( volatile Uint32* )( PLL2_BASE + 0x138 ) // PLL Controller Command Register
#define PLL2_PLLSTAT *( volatile Uint32* )( PLL2_BASE + 0x13C ) // PLL Controller Status Register
#define PLL2_ALNCTL *( volatile Uint32* )( PLL2_BASE + 0x140 ) // PLL Controller Clock Align Control Register
#define PLL2_DCHANGE *( volatile Uint32* )( PLL2_BASE + 0x144 ) // PLLDiv Ratio Change status Register
#define PLL2_CKEN *( volatile Uint32* )( PLL2_BASE + 0x148 ) // Clock Enable Control Register
#define PLL2_CKSTAT *( volatile Uint32* )( PLL2_BASE + 0x14C ) // Clock Status Register
#define PLL2_SYSTAT *( volatile Uint32* )( PLL2_BASE + 0x150 ) // SYSCLK Status Register
#define PLL2_PLLDIV4 *( volatile Uint32* )( PLL2_BASE + 0x160 ) // PLL Controller Div4 Register
#define PLL2_PLLDIV5 *( volatile Uint32* )( PLL2_BASE + 0x164 ) // PLL Controller Div5 Register
#define PLL2_PLLDIV6 *( volatile Uint32* )( PLL2_BASE + 0x168 ) // PLL Controller Div6 Register
#define PLL2_PLLDIV7 *( volatile Uint32* )( PLL2_BASE + 0x16C ) // PLL Controller Div7 Register
#define PLL2_PLLDIV8 *( volatile Uint32* )( PLL2_BASE + 0x170 ) // PLL Controller Div8 Register
/* ------------------------------------------------------------------------ *
* *
* PSC ( Power and Sleep Controller ) *
* *
* ------------------------------------------------------------------------ */
#define PSC_BASE 0x01C41000
#define PSC_EPCPR *( volatile Uint32* )( PSC_BASE + 0x070 )
#define PSC_PTCMD *( volatile Uint32* )( PSC_BASE + 0x120 )
#define PSC_PTSTAT *( volatile Uint32* )( PSC_BASE + 0x128 )
#define PSC_PDSTAT0 *( volatile Uint32* )( PSC_BASE + 0x200 )
#define PSC_PDSTAT1 *( volatile Uint32* )( PSC_BASE + 0x204 )
#define PSC_PDCTL0 *( volatile Uint32* )( PSC_BASE + 0x300 )
#define PSC_PDCTL1 *( volatile Uint32* )( PSC_BASE + 0x304 )
#define PSC_MDSTAT_BASE ( PSC_BASE + 0x800 )
#define PSC_MDCTL_BASE ( PSC_BASE + 0xA00 )
/* Power Domains */
#define ALWAYSON_POWER_DOMAIN 0
#define DSP_POWER_DOMAIN 1
/* Module Domains */
#define LPSC_VPSSMSTR 0 // VPSS Master
#define LPSC_VPSSSLV 1 // VPSS Slave
#define LPSC_TPCC 2 // TPCC
#define LPSC_TPTC0 3 // TPTC0
#define LPSC_TPTC1 4 // TPTC1
#define LPSC_EMAC 5 // EMAC
#define LPSC_EMAC_WRAPPER 6 // EMAC WRAPPER
#define LPSC_MDIO 7 // MDIO
#define LPSC_IEEE1394 8 // IEEE1394
#define LPSC_USB 9 // USB
#define LPSC_ATA 10 // ATA
#define LPSC_VLYNQ 11 // VLYNQ
#define LPSC_UHPI 12 // UHPI
#define LPSC_DDR_EMIF 13 // DDR_EMIF
#define LPSC_AEMIF 14 // AEMIF
#define LPSC_MMC_SD 15 // MMC_SD
#define LPSC_MEMSTICK 16 // MEMSTICK
#define LPSC_McBSP 17 // McBSP
#define LPSC_I2C 18 // I2C
#define LPSC_UART0 19 // UART0
#define LPSC_UART1 20 // UART1
#define LPSC_UART2 21 // UART2
#define LPSC_SPI 22 // SPI
#define LPSC_PWM0 23 // PWM0
#define LPSC_PWM1 24 // PWM1
#define LPSC_PWM2 25 // PWM2
#define LPSC_GPIO 26 // GPIO
#define LPSC_TIMER0 27 // TIMER0
#define LPSC_TIMER1 28 // TIMER1
#define LPSC_TIMER2 29 // TIMER2
#define LPSC_SYSTEM_SUBSYS 30 // SYSTEM SUBSYSTEM
#define LPSC_ARM 31 // ARM
#define LPSC_SCR2 32 // SCR2
#define LPSC_SCR3 33 // SCR3
#define LPSC_SCR4 34 // SCR4
#define LPSC_CROSSBAR 35 // CROSSBAR
#define LPSC_CFG27 36 // CFG27
#define LPSC_CFG3 37 // CFG3
#define LPSC_CFG5 38 // CFG5
#define LPSC_GEM 39 // GEM
#define LPSC_IMCOP 40 // IMCOP
/* ------------------------------------------------------------------------ *
* *
* System Controller *
* *
* ------------------------------------------------------------------------ */
#define PINMUX_BASE 0x01C40000
#define PINMUX0 *( volatile Uint32* )( PINMUX_BASE + 0x0 )
#define PINMUX1 *( volatile Uint32* )( PINMUX_BASE + 0x4 )
#define VDD3P3V_PWDN *( volatile Uint32* )0x01C40048
/* ------------------------------------------------------------------------ *
* *
* UART Controller *
* *
* ------------------------------------------------------------------------ */
#define UART0_BASE 0x01C20000
#define UART0_RBR *( volatile Uint32* )( UART0_BASE + 0x00 )
#define UART0_THR *( volatile Uint32* )( UART0_BASE + 0x00 )
#define UART0_IER *( volatile Uint32* )( UART0_BASE + 0x04 )
#define UART0_IIR *( volatile Uint32* )( UART0_BASE + 0x08 )
#define UART0_FCR *( volatile Uint32* )( UART0_BASE + 0x08 )
#define UART0_LCR *( volatile Uint32* )( UART0_BASE + 0x0c )
#define UART0_MCR *( volatile Uint32* )( UART0_BASE + 0x10 )
⌨️ 快捷键说明
复制代码
Ctrl + C
搜索代码
Ctrl + F
全屏模式
F11
切换主题
Ctrl + Shift + D
显示快捷键
?
增大字号
Ctrl + =
减小字号
Ctrl + -