davincievm_pll.c

开发环境CCS3.2,为TI最新处理器TMS320DM6446的网卡驱动程序源码

/*
 *  Copyright 2005 by Spectrum Digital Incorporated.
 *  All rights reserved. Property of Spectrum Digital Incorporated.
 *
 *  Not for distribution.
 */

/*
 *  Board Setup ( for ARM and/or DSP )
 *
 */

#include "davincievm_pll.h"

/* ------------------------------------------------------------------------ *
 *                                                                          *
 *  DAVINCIEVM_enablePll1( clock_source, pll_mult )                         *
 *                                                                          *
 *      clock_source    <- 0: Onchip Oscillator                             *
 *                         1: External Oscillator                           *
 *                                                                          *
 *      pll_mult        <- 16: Normal mode ( For PLL1 )                     *
 *                         22: Turbo mode  ( For PLL1 )                     *
 *                         X:  Range 0-63                                   *
 *                                                                          *
 * ------------------------------------------------------------------------ */
Int16 DAVINCIEVM_enablePll1( Uint16 clock_source, Uint16 pll_mult )
{
    volatile Uint32* pll_ctl;
    volatile Uint32* pll_pllm;

    clock_source &= 0x00000001;         // Range [0:OSCIN 1:CLKIN]
    pll_mult     &= 0x0000003F;         // Range [0-63]


    pll_ctl  = ( volatile Uint32* )PLL1_PLLCTL;
    pll_pllm = ( volatile Uint32* )PLL1_PLLM;


    *pll_ctl &= 0xFFFFFEFF;             // Clear clock source mode
    *pll_ctl |= ( clock_source << 8 );  // Set clock source mode
    *pll_ctl &= 0xFFFFFFDE;             // Set PLL to Bypass mode

    DAVINCIEVM_wait( 0x20 );            // wait for PLL o switch to bypass clock

    *pll_ctl &= 0xFFFFFFF7;             // Reset PLL
    *pll_ctl |= 0x00000010;             // Disable PLL
    *pll_ctl &= 0xFFFFFFFD;             // Power up PLL
    *pll_ctl &= 0xFFFFFFEF;             // Enable PLL

    *pll_pllm = pll_mult;               // Set PLL multiplier

    /*
     *  For PLL1: DSP, ARM, VBUS, ImCop, CFG are fixed
     *
     *  For PLL2: DDR2 and VPBE are programmable
     */

    DAVINCIEVM_wait( 0x100 );           // Wait for PLL to Reset
    *pll_ctl |= 0x00000008;             // Release PLL from Reset
    DAVINCIEVM_wait( 0x1000 );          // Wait for PLL to LOCK
    *pll_ctl |= 0x00000001;             // Set PLL to PLL mode

    return 0;
}

/* ------------------------------------------------------------------------ *
 *                                                                          *
 *  DAVINCIEVM_enablePll2( clock_source, pll_mult, divider1, divider2 )     *
 *                                                                          *
 *      clock_source    <- 0: Onchip Oscillator                             *
 *                         1: External Oscillator                           *
 *                                                                          *
 *      pll_mult        <- 16: Normal mode ( For PLL1 )                     *
 *                         22: Turbo mode  ( For PLL1 )                     *
 *                         X:  Range 0-63                                   *
 *                                                                          *
 *      divider1        <- VPSS divider ( For PLL2 )                        *
 *                                                                          *
 *      divider2        <- DDR2 divider ( For PLL2 )                        *
 *                                                                          *
 * ------------------------------------------------------------------------ */
Int16 DAVINCIEVM_enablePll2( Uint16 clock_source, Uint16 pll_mult,
                             Uint16 divider1, Uint16 divider2 )
{
    volatile Uint32* pll_ctl;
    volatile Uint32* pll_pllm;
    volatile Uint32* pll_div1;
    volatile Uint32* pll_div2;
    volatile Uint32* pll_cmd;
    volatile Uint32* pll_stat;

    clock_source &= 0x00000001;         // Range [0:OSCIN 1:CLKIN]
    pll_mult     &= 0x0000003F;         // Range [0-63]

    pll_ctl  = ( volatile Uint32* )PLL2_PLLCTL;
    pll_pllm = ( volatile Uint32* )PLL2_PLLM;
    pll_div1 = ( volatile Uint32* )PLL2_PLLDIV1;
    pll_div2 = ( volatile Uint32* )PLL2_PLLDIV2;
    pll_cmd  = ( volatile Uint32* )PLL2_PLLCMD;
    pll_stat = ( volatile Uint32* )PLL2_PLLSTAT;

    *pll_ctl &= 0xFFFFFEFF;             // Clear clock source mode
    *pll_ctl |= ( clock_source << 8 );  // Set clock source mode
    *pll_ctl &= 0xFFFFFFDE;             // Set PLL to Bypass mode

    DAVINCIEVM_wait( 0x20 );            // wait for PLL o switch to bypass clock

    *pll_ctl &= 0xFFFFFFF7;             // Reset PLL
    *pll_ctl |= 0x00000010;             // Disable PLL
    *pll_ctl &= 0xFFFFFFFD;             // Power up PLL
    *pll_ctl &= 0xFFFFFFEF;             // Enable PLL

    *pll_pllm = pll_mult;               // Set PLL multiplier

    /*
     *  For PLL1: DSP, ARM, VBUS, ImCop, CFG are fixed
     *
     *  For PLL2: DDR2 and VPBE are programmable
     */
    *pll_div1 = divider1;	            // Set PLL dividers
    *pll_div2 = divider2;
    *pll_div1 |= 0x00008000;            // Enable PLL dividers
    *pll_div2 |= 0x00008000;

    *pll_cmd |= 0x00000001;             // Set phase alignment
    while( ( *pll_stat & 1 ) == 1 );    // Wait for operation to finish

    DAVINCIEVM_wait( 0x100 );           // Wait for PLL to Reset
    *pll_ctl |= 0x00000008;             // Release PLL from Reset
    DAVINCIEVM_wait( 0x1000 );          // Wait for PLL to LOCK
    *pll_ctl |= 0x00000001;             // Set PLL to PLL mode

    return 0;
}