bootloader.s.bak

移植Nuclues_RTC到coldfire5307在diab下编译通过

IMMaddr:	equ	0x10000000
SDRAMaddr:	equ	0x00000000
SDRAMsize:	equ	0x02000000	;;32M bytes
SRAMaddr:	equ	0x01000000
SRAMsize:	equ	(4 * 1024)	;;4K

_VECTOR_TABLE	equ	0x00000000

DATA_LENGTH         	equ     0x00400000 	;	length of code to loaded to DRam , 4M assumed
FLASH_CODE_ADDR         equ     0xFF020000	;	main.dwn code image start address in flash 
DRAM_START		equ	0x00001000	;	dram start address


;flash after written
;0xff000000->SEG00-->start address & SP
;0xff010000->SEG01-->bootloader
;0xff020000->SEG02-->linux execucive code
;bootloader will copy SEG02 to dram from 0x00001000, then jmp to there.


	XDEF start
start:
_asm_startmeup:

		move.w		#0x2700,SR

		move.l		#_VECTOR_TABLE,d0
		movec		d0,VBR

		move.l		#SRAMaddr+0x21,d0
		movec		d0,RAMBAR

		move.l		#IMMaddr+0x1,d0
		movec		d0,MBAR

SDRAM_START:		
;DRAM_INIT1:		
		move.w          #0x822A, D0
		move.w          D0, 0x10000100.L       ;DCR


;to init the BANK0
;16MB/32 bits
;From 0x00000000->0x00ffffff
		move.l          #0x00001304, D0
		move.l          D0, 0x10000108.L       ;DACR0
		
		move.l          #0x00FC0001, D0
		move.l          D0, 0x1000010C.L       ;DCMR0
		
		move.l          #0x0000130C, D0
		move.l          D0, 0x10000108.L       ;DACR0
		
		move.l          #0xA5A59696, D0
		move.l          D0, 0x00000400.L       ;dummy write
		
		move.l          #0x00009304, D0
		move.l          D0, 0x10000108.L       ;DACR0

;to init the BANK1
;16MB/32bits
;From 0x01000000->0x01ffffff
		move.l          #0x01001304, D0
		move.l          D0, 0x10000110.L       ;DACR1
		
		move.l          #0x00FC0001, D0
		move.l          D0, 0x10000114.L       ;DCMR1
		
		move.l          #0x0100130C, D0
		move.l          D0, 0x10000110.L       ;DACR1
		
		move.l          #0xA5A59696, D0
		move.l          D0, 0x01000400.L       ;dummy write
		
		move.l          #0x01009304, D0
		move.l          D0, 0x10000110.L       ;DACR1
		
		
;CS_INIT:
		move.w          #0xFF00, D0
		move.w          D0, 0x10000080.L       ;CSAR0		
		move.w          #0x1D80, D0
		move.w          D0, 0x1000008A.L       ;CSCR0		
		move.l          #0x00FF0001, D0
		move.l          D0, 0x10000084.L       ;CSMR0
		
		move.w          #0xff00, D0
		move.w          D0, 0x1000008C.L       ;CSAR1		
		move.w          #0x2980, D0
		move.w          D0, 0x10000096.L       ;CSCR1		
		move.l          #0x007F0000, D0
		move.l          D0, 0x10000090.L       ;CSMR1
		
		move.w          #0x3000, D0
		move.w          D0, 0x10000098.L       ;CSAR2		
		move.w          #0x1140, D0
		move.w          D0, 0x100000A2.L       ;CSCR2		
		move.l          #0x00FF0000, D0
		move.l          D0, 0x1000009C.L       ;CSMR2
		
		move.w          #0x4000, D0
		move.w          D0, 0x100000A4.L       ;CSAR3		
		move.w          #0x11A0, D0
		move.w          D0, 0x100000AE.L       ;CSCR3		
		move.l          #0x007F0000, D0
		move.l          D0, 0x100000A8.L       ;CSMR3
		
		move.w          #0xff00, D0
		move.w          D0, 0x100000B0.L       ;CSAR4		
		move.w          #0x3CA0, D0
		move.w          D0, 0x100000BA.L       ;CSCR4		
		move.l          #0x00FF0000, D0
		move.l          D0, 0x100000B4.L       ;CSMR4
		
		move.w          #0xff00, D0
		move.w          D0, 0x100000BC.L       ;CSAR5		
		move.w          #0x29A0, D0
		move.w          D0, 0x100000C6.L       ;CSCR5		
		move.l          #0x00FF0000, D0
		move.l          D0, 0x100000C0.L       ;CSMR5
		
		move.w          #0xff00, D0
		move.w          D0, 0x100000C8.L       ;CSAR6		
		move.w          #0x2980, D0
		move.w          D0, 0x100000D2.L       ;CSCR6		
		move.l          #0x007F0000, D0
		move.l          D0, 0x100000CC.L       ;CSMR6
		
		move.w          #0xff00, D0
		move.w          D0, 0x100000D4.L       ;CSAR7		
		move.w          #0x2980, D0
		move.w          D0, 0x100000DE.L       ;CSCR7		
		move.l          #0x007F0000, D0
		move.l          D0, 0x100000D8.L       ;CSMR7


		
;DRAM_INIT2:
		
		move.l          #0x00009344, D0
		move.l          D0, 0x10000108.L       ;DACR0
		
		move.l          #0xA5A59696, D0
		move.l          D0, 0x00000400.L       ;   
		
		move.l          #0x01009344, D0
		move.l          D0, 0x10000108.L       ;DACR1
		
		move.l          #0xA5A59696, D0
		move.l          D0, 0x01000400.L       ;
		
		
;  clear SRAM
;		lea.l		SRAMaddr,A0
;		move.l		#1024,D0
;SRAM_INIT_LOOP:
;		clr.l		(A0)+
;		subq.l		#1,D0
;		bne.b		SRAM_INIT_LOOP


		nop		  
		nop

		nop
		nop
		nop
		move.w #0x2700,SR		;/* mask off IRQ's */
		clr.l d0
		movec d0,ACR0			;/* ACR0 off */
		movec d0,ACR1			;/* ACR1 off */
		move.l #0x01000000,d0           ;/* Invalidate and disable cache */
		movec d0,CACR	
		nop
		nop
		nop


		MOVE.L	#0X0000C000,D0		;CACHE THE SDRAM   , from 0x00000000, WRITE through
		MOVEC	D0,ACR0
		
		
		MOVE.L	#0X0100C000,D0		;CACHE THE SDRAM   , from 0x01000000, WRITE through
		MOVEC	D0,ACR1
				
		MOVE.L	#0xa1000200,D0		;ENABLE CACHE ,with BUFFER, default  no cache precise
		MOVEC	D0,CACR
		nop
		nop
		nop
		nop
		nop
		nop
		nop
		nop
		nop
		nop
		nop
		nop
		nop
		nop


;load main.dwn code in flash to DRam and jump PC to DRam
	move.l  #DATA_LENGTH, D1
	move.l  #FLASH_CODE_ADDR, A0
	move.l  #DRAM_CODE_ADDR, A1
LOAD_NOT_OK:
	move.b  (A0)+, D0
	move.b  D0,    (A1)+
	subq.l  #1,    D1
	BNE     LOAD_NOT_OK
	JMP     DRAM_START
;end of load and jump