cache.s

coldfire5307的bootloader 将程序写入flash

;this subrouting to Enable cache of 5307
		XDEF _cpu_cache_disable
		XDEF _EnableCache
		XDEF _mcf5307_wr_cacr
		XDEF _mcf5307_wr_acr0
		XDEF _mcf5307_wr_acr1
		
		

;/********************************************************************
; *	Routine to cleanly flush the cache, pushing all lines and 
; *	invalidating them.  This must be done to change the cache when 
; *	we have been operating in copyback mode (i.e. writes to a copyback 
; *	region are probably resident in the cache and not in the main store).
; */
_cpu_cache_flush:
	nop			;/* synchronize - flush store buffer */

	moveq.l #0,d0		;/* init line counter */
	moveq.l #0,d1		;/* init set counter */
	move.l d0,a0		;/* init An */

flushloop:
	cpushl (a0)		;/* push cache line a0 */
	add.l #0x0010,a0        ;/* increment setindex by 1 */
	addq.l #1,d1		;/* increment set counter */
	cmpi.l #128,d1		;/* are sets for this line done? */
	bne  flushloop

	moveq.l #0,d1		;/* set counter to zero again */
	addq.l #1,d0		;/* increment to next line */
	move.l d0,a0		;/* set 0, line d0 into a0 as per cpushl */
	cmpi.l #4,d0
	bne  flushloop

	rts

;/********************************************************************
; *	Routine to disable to cache completely
; *	THIS ROUTINE DISABLES IRQ's -- be warned
; */
_cpu_cache_disable:
	nop
	move.w #0x2700,SR		;/* mask off IRQ's */
;	jsr _cpu_cache_flush	        ;/* flush the cache completely */
	clr.l d0
	movec d0,ACR0			;/* ACR0 off */
	movec d0,ACR1			;/* ACR1 off */
	move.l #0x01000000,d0           ;/* Invalidate and disable cache */
	movec d0,CACR			
	rts



	
	
;/********************************************************************
; * These routines write to the special purpose registers in the ColdFire
; * core.  Since these registers are write-only in the supervisor model,
; * no corresponding read routines exist.
; */


mcf5307_wr_cacr:
_mcf5307_wr_cacr:
    move.l  4(sp),d0
    dc.l    0x4e7b0002         ;/* movec d0,cacr	 */
    nop
    rts

mcf5307_wr_acr0:
_mcf5307_wr_acr0:
    move.l  4(sp),d0
    dc.l    0x4e7b0004        ;/* movec d0,ACR0	*/
    nop
    rts

mcf5307_wr_acr1:
_mcf5307_wr_acr1:
    move.l  4(sp),d0
    dc.l    0x4e7b0005       ;/* movec d0,ACR1	*/
    nop
    rts	






_EnableCache:
		
		MOVE.L	#0X0000C000,D0		;CACHE THE SDRAM   ,WRITE through
		MOVEC	D0,ACR0
		
		
		MOVE.L	#0X00,D0		;CACHE THE SDRAM   ,WRITE through
		MOVEC	D0,ACR1
				
		MOVE.L	#0xa1000200,D0		;ENABLE CACHE ,with BUFFER, default  no cache precise
		MOVEC	D0,CACR
		nop
		nop
		nop
		nop
		nop
		nop
		nop
		nop
		nop
		nop
		nop
		nop
		nop
		nop
		
		
		RTS