main.c

transplant uc/os2 on coldfire5307 编译通过

/*  main.c
 *
 *	Motorola Coldfire MCF5307 port to MicroC/OS-II
 *
 *  Ross Berteig
 *  Cheshire Engineering Corp
 *  650 Sierra Madre Villa, Suite 201
 *  Pasadena  CA 91107
 *  [phone]       [phone] FAX
 *  [e-mail], www.CheshireEng.com
 *
 *  Copyright (C) 1998 Cheshire Engineering Corporation.
 *  Based on a port to uCOS version 1.x by David Fiddes.
 *  Portions Copyright (C) 1997 David Fiddes, [e-mail]
 *  Anything that no longer works is probably not his fault.
 *
 *  This module provides the C main entry point and general
 *  initialization of the Arnewsh SBC5307 Evaluation Board.
 *
 *  Builds with the Diab Data C compiler, tested under SDS SingleStep.
 *  Should work as S-record download into dBUG also, but will be
 *  harder to prove to work.
 */

#include "includes.h"			/* uCOS definitions */
#include <stdio.h>
#include <string.h>


WORD	msg_RXDOk = 0;
BYTE		RXDBuf[30];
BYTE		RXDCnt = 0;

/*  EarlyInit
 *
 *	Place for hardware and other intialization to be done
 *  after C runtime initializations, but before MicroC/OS-II
 *  is started.
 *
 *  Notice that this assumes that some other piece of system code
 *  has already made the SDRAM work.  This could either be the
 *  dBUG monitor, a configuration file for SingleStep, or a
 *  custom boot loader.
 */ 
 void InitUART11(MCF5307_IMM *imm);
void UART1ReadPacket(MCF5307_IMM *imm);
void UART1WritePacket(MCF5307_IMM *imm, unsigned char*pkt, WORD len);



void EarlyInit()
{
    register MCF5307_IMM *imm = &__MBAR;

    // Mask out all interrupts
    imm->sim.IMR = ~0;

    // Set parallel port as 2 bytes of useful bits, all outputs
    imm->sim.PAR = 0xffff;
    imm->parallel_port.PADDR = 0x00ff;
    imm->parallel_port.PADAT = 0;

    // magic settings needed for 5307 to correctly stack exceptions.
    // Without this setting, 0x00000000 is occasionally used as the
    // return address in the exception frame, causing bad things to
    // happen.
    imm->sim.MPARK = MCF5307_SIM_MPARK_EARBCTRL | MCF5307_SIM_MPARK_SHOWDATA;

    // Set Chip Select system to match dBUG monitor and linker config
    //
    // This must be done so that the uC/OS kernel, when downloaded and
    // run from SingleStep, will be able to count on the correct PC
    // value in stacked exception frames.  Setting up CS0 here is sufficient.
    // So is setting MPARK to include EARBCTRL|SHOWDATA as shown later.
    
    // CS0:  1 Mb at 0xffe00000 - 0xffefffff, WS=3, AA=1, PS=16bit, no bursts
    imm->cs.CSAR0 = 0xFFE0;
    imm->cs.CSMR0 = 0x000F0001;
    imm->cs.CSCR0 = 0x0D80;

    // CS1: unused, V=0
    imm->cs.CSAR1 = 0x0080;	// 0xffff
    imm->cs.CSMR1 = 0x00000000;	// 0x00000001
    imm->cs.CSCR1 = 0x0100;

    // CS2 - CS7 are 2 Mb each, based at 0xfe400000.
    imm->cs.CSBAR = 0xFE;
    imm->cs.CSMR2 = 0x00000001;	// CS2: Valid, 32bit, AA=1, WS=0
    imm->cs.CSCR2 = 0x0140;
    imm->cs.CSMR3 = 0x00000015; // CS3: Valid, 16bit, AA=1, SC, UC
    imm->cs.CSCR3 = 0x0080;
    imm->cs.CSMR4 = 0x00000001; // CS4: Valid, 16bit, AA=1, SC, UC
    imm->cs.CSCR4 = 0x0080;
    imm->cs.CSMR5 = 0x0000001f; // 0x0000001F;
    imm->cs.CSCR5 = 0x0100;
    imm->cs.CSMR6 = 0x0000001f;
    imm->cs.CSCR6 = 0x0100;
    imm->cs.CSMR7 = 0x0000001f;
    imm->cs.CSCR7 = 0x0100;

    // Interrupt controls to match dBUG
    imm->sim.AVCR = 0xFF;
    imm->sim.ICR0 = 0x9E;
    imm->sim.ICR1 = 0x97;
    imm->sim.ICR2 = 0x95;
    imm->sim.ICR3 = 0x8C;
    imm->sim.ICR4 = 0x8E;
    imm->sim.ICR5 = 0x8D;
    imm->sim.ICR6 = 0x88;
    imm->sim.ICR7 = 0x89;
    imm->sim.ICR8 = 0x8A;
    imm->sim.ICR9 = 0x8B;
    imm->sim.ICR10 = 0x84;
    imm->sim.ICR11 = 0x86;
    
}

/*  HookOSVectors()
 *
 *	Set the vectors required for uC/OS operation.
 */

void HookOSVectors()
{
    ADDRESS *vect = (ADDRESS *)0x00000000;
    
    // Hook required vectors:
    vect[14] = (ADDRESS)&CPUFormatError; /* Format Error Exception */
    vect[24+5] = (ADDRESS)&OSTickISR;	/* AutoVector 5 - Timer tick */
    vect[32+14] = (ADDRESS)&OSCtxSw;	/* Trap 14 - Do a context switch */
}


/*  StartTicking
 *
 *	Setup and release the TIMER1 as a periodic interrupt source.
 *  We need a heartbeat for the uC/OS task scheduler to use for
 *  task preemption.  This should have a 10 ms period to match the
 *  declaration of OS_TICKS_PER_SEC in OS_CFG.h.
 *
 *  The frequency is 100Hz =  BCLK / (1 or 16) / prescale / reference
 *	=  45 MHz / 1 / 45 / 10000
 */

void StartTicking()
{
    register MCF5307_IMM *imm = &__MBAR;

    // disable timer1 interrupts
    imm->sim.IMR |= MCF5307_SIM_IMR_TIMER1;

    // reset the timer
    imm->timer.TMR1 = MCF5307_TIMER_TMR_RST; // enable
    imm->timer.TMR1 = 0x0000;		     // reset

    // setup timer
    imm->timer.TMR1 = MCF5307_TIMER_TMR_RST; // enable
    imm->timer.TMR1 = MCF5307_TIMER_TMR_PS(45) |	// Prescale
		      MCF5307_TIMER_TMR_CE_NONE |	// No capture
		      MCF5307_TIMER_TMR_ORI |		// Output Ref Int enable
		      MCF5307_TIMER_TMR_FRR |		// Free run restart
		      MCF5307_TIMER_TMR_CLK_STOP |	// Stopped clock
		      MCF5307_TIMER_TMR_RST;		// Enabled
    imm->timer.TCN1 = 0;			// zero count
    imm->timer.TRR1 = 10000;			// 10 msec period

    // start timer
    imm->timer.TMR1 |= MCF5307_TIMER_TMR_CLK_MSCLK;

    //enable timer1 interrupts
    imm->sim.ICR1 = MCF5307_SIM_ICR_AVEC |
		    MCF5307_SIM_ICR_IL(5) |
		    0x0003; //MCF5307_SIM_ICR_HI2 
    imm->sim.IMR &= ~MCF5307_SIM_IMR_TIMER1;
}


/*  StartupTask
 *
 *	Task function for system startup task created in main().  Its
 *  primary duty is to enable the tick interrupt so that the task
 *  scheduler will get its heartbeats. This must be done after at least
 *  one task is created and running (e.g. this task) to eliminate a
 *  race condition in the kernel. 
 */

void StartupTask(void *data)
{     extern void StartupMain(void);

   unsigned short d;	
unsigned short LedOut;
register MCF5307_IMM *imm = &__MBAR;
	imm->sim.PAR = 0xff00;
    imm->parallel_port.PADDR = 0x00ff;
    imm->parallel_port.PADAT = 0;

 	


 OS_ENTER_CRITICAL();
    StartTicking();
    OS_EXIT_CRITICAL();
	
    OSTimeDlyHMSM(0,0,2,0);

    StartupMain();
    OSTaskDel(OS_PRIO_SELF);
}

/*  main
 *
 *	Where everything starts.
 *
 *	Called out of Diab's crt0.s.  We assume that we are running
 *  from downloaded code in the eval board.  This means that basic
 *  hardware services such as the DRAM are present and initialized.
 *  We will call a pro-forma hardware initialization routine to setup
 *  our timer tick and any other services we need not supplied by the
 *  dBUG initialization.
 */

void main()
{	  register MCF5307_IMM *imm = &__MBAR;
	unsigned char Hello[]="hello!welcome ucos-II  !!!!! Now initmcf5307\r\n";

	OS_STK StartupTaskStack[1024];

    memset(StartupTaskStack, 0x55, sizeof(StartupTaskStack));

    EarlyInit();
	InitUART11(imm) ;
    HookOSVectors();
	
    OSInit();
		UART1WritePacket(imm, Hello, sizeof(Hello)+1);

    OSTaskCreate(StartupTask,
		 (void *)0,
		 &StartupTaskStack[1023],
		 OS_LOWEST_PRIO - 4);

    OSStart();

    /*
     * Can't get here, but plug the possible leak with another
     * HALT instruction just in case.
     */

    asm (" HALT ");
}

void InitUART11(MCF5307_IMM *imm)
{
	imm->uart1.UCR1=0x10;    /*to reset the Mode Register Pointer*/
	imm->uart1.UCR1=0x20;    /*to reset the Receiver*/
	imm->uart1.UCR1=0x30;    /*to reset the Transimitter*/
	imm->uart1.UCR1=0x40;    /*to reset the Error Stauts*/
	imm->uart1.UCR1=0x50;    /*to reset the Break Change Interrupt*/
	
	imm->uart1.UMR11_UMR21=0x13;   //no Parity , 8bits
	imm->uart1.UMR11_UMR21=0x07;   //mode Normal,one stop bit
	
	imm->uart1.USR1_UCSR1=0xdd;  //use Timer as Clock
	
	imm->uart1.UISR1_UIMR1=0x00;  //Disenable Interrupt
	
	imm->uart1.UBG11=0x00;
	imm->uart1.UBG21=0x92;        //bus Freq=45MHz,9600 bps
	
	imm->uart1.UCR1=0x10;    /*to reset the Mode Register Pointer*/
	imm->uart1.UCR1=0x20;    /*to reset the Receiver*/
	imm->uart1.UCR1=0x30;    /*to reset the Transimitter*/
	imm->uart1.UCR1=0x05;    /*to Enable Receiver & Transmitter*/
	
	imm->uart1.UISR1_UIMR1=0x02;  //Enable Interrupt 
	 
	imm->sim.ICR4=0x84;           //enable auto vect. ,level 1  ,to vect offset 0x64
	
	imm->sim.IMR=(0x0000
                |MCF5307_SIM_IMR_DMA3
 	        |MCF5307_SIM_IMR_DMA2
 		|MCF5307_SIM_IMR_DMA1
 		|MCF5307_SIM_IMR_DMA0
 		|MCF5307_SIM_IMR_UART2
 		|MCF5307_SIM_IMR_UART1
 		|MCF5307_SIM_IMR_MBUS
 		|MCF5307_SIM_IMR_TIMER2
 		|MCF5307_SIM_IMR_TIMER1
 		|MCF5307_SIM_IMR_SWT
 		|MCF5307_SIM_IMR_EINT7
 		|MCF5307_SIM_IMR_EINT6
 		|MCF5307_SIM_IMR_EINT5
 		|MCF5307_SIM_IMR_EINT4
 		|MCF5307_SIM_IMR_EINT3
 		|MCF5307_SIM_IMR_EINT2                  //enable net card
 		|MCF5307_SIM_IMR_EINT1 
 	       );  
	
	//asm("		move.w		#0x2000,SR      ");    //enable interrupt      
	
	
}

/* ------------------------------------------------------------------
	Function: void InitUART1(MCF5307_IMM *imm)						]
	Comment: Initialze UART1 of MCF5307								]
			 For more information,refer to file MCF5307TR_DUART.PDF ]
-------------------------------------------------------------------*/
void UART1WritePacket(MCF5307_IMM *imm, unsigned char*pkt, WORD len)
{
	WORD i;
	for(i = 0; i < len; i++)
	{
		imm->uart1.URB1_UTB1 = pkt[i];
		while (!(imm->uart1.USR1_UCSR1 && 8));			// Wait until character is sent
	}
}

/* ------------------------------------------------------------------
	Function: void UART1ReadPacket(MCF5307_IMM *imm)				]
	Comment: Read a packet from UART1								]
-------------------------------------------------------------------*/
void UART1ReadPacket(MCF5307_IMM *imm)
{
	volatile BYTE buf;
	
	if(imm->uart1.USR1_UCSR1&1) 
	{
		buf = imm->uart1.URB1_UTB1;
		switch(buf)
		{
			case 's':
			{
				RXDCnt = 0;
				RXDBuf[0] = 's';
				break;
			}
			case 'n':
			{
				RXDCnt++;
				RXDBuf[RXDCnt] = 'n';
				msg_RXDOk = 1;
				break;
			}
			default:
			{
				RXDCnt++;
				RXDBuf[RXDCnt] = buf;
				break;
			}		
		}
	}
}

//Ready for Receive Data
/*void Uart1_Ready_Receive()
{
//Uart1_RxCompleted=0x00;


}*/