dsp56f807.h

codewarrior dsp 56807 中断编程实现灯闪烁,有详细的注释

#define PWMB_PWMVAL5	PWMB_BASE + 0xb
#define PWMB_PMDEADTM	PWMB_BASE + 0xc
#define PWMB_PMDISMAP1	PWMB_BASE + 0xd
#define PWMB_PMDISMAP2	PWMB_BASE + 0xe
#define PWMB_PMDCFG		PWMB_BASE + 0xf
#define PWMB_PMCCR		PWMB_BASE + 0x10
#define PWMB_PMPORT		PWMB_BASE + 0x11

/* Quadrature Decoder */
#define DEC0_BASE	0x1240

#define QD0_DECCR	DEC0_BASE + 0x0
#define QD0_FIR		DEC0_BASE + 0x1
#define QD0_WTR		DEC0_BASE + 0x2
#define QD0_POSD	DEC0_BASE + 0x3
#define QD0_POSDH	DEC0_BASE + 0x4
#define QD0_REV		DEC0_BASE + 0x5
#define QD0_REVH	DEC0_BASE + 0x6
#define QD0_UPOS	DEC0_BASE + 0x7
#define QD0_LPOS	DEC0_BASE + 0x8
#define QD0_UPOSH	DEC0_BASE + 0x9
#define QD0_LPOSH	DEC0_BASE + 0xa
#define QD0_UIR		DEC0_BASE + 0xb
#define QD0_LIR		DEC0_BASE + 0xc
#define QD0_IMR		DEC0_BASE + 0xd
#define QD0_TSTREG	DEC0_BASE + 0xe

#define DEC1_BASE	0x1250

#define QD1_DECCR	DEC1_BASE + 0x0
#define QD1_FIR		DEC1_BASE + 0x1
#define QD1_WTR		DEC1_BASE + 0x2
#define QD1_POSD	DEC1_BASE + 0x3
#define QD1_POSDH	DEC1_BASE + 0x4
#define QD1_REV		DEC1_BASE + 0x5
#define QD1_REVH	DEC1_BASE + 0x6
#define QD1_UPOS	DEC1_BASE + 0x7
#define QD1_LPOS	DEC1_BASE + 0x8
#define QD1_UPOSH	DEC1_BASE + 0x9
#define QD1_LPOSH	DEC1_BASE + 0xa
#define QD1_UIR		DEC1_BASE + 0xb
#define QD1_LIR		DEC1_BASE + 0xc
#define QD1_IMR		DEC1_BASE + 0xd
#define QD1_TSTREG	DEC1_BASE + 0xe


/* Interrupt controller */
#define ITCN_BASE	0x1260

#define GPR0	ITCN_BASE + 0x0
#define GPR1	ITCN_BASE + 0x1
#define GPR2	ITCN_BASE + 0x2
#define GPR3	ITCN_BASE + 0x3
#define GPR4	ITCN_BASE + 0x4
#define GPR5	ITCN_BASE + 0x5
#define GPR6	ITCN_BASE + 0x6
#define GPR7	ITCN_BASE + 0x7
#define GPR8	ITCN_BASE + 0x8
#define GPR9	ITCN_BASE + 0x9

#define GPR10	ITCN_BASE + 0xa /// Interrupt Controller Registers Address Map++++++++++++++++++++
///Group Priority Register 10 // Group Priority Register 10 Address Offset $A
#define GPR11	ITCN_BASE + 0xb
#define GPR12	ITCN_BASE + 0xc
#define GPR13	ITCN_BASE + 0xd
#define GPR14	ITCN_BASE + 0xe
#define GPR15	ITCN_BASE + 0xf
#define TIRQ0	ITCN_BASE + 0x10
#define TIRQ1	ITCN_BASE + 0x11
#define TIRQ2	ITCN_BASE + 0x12
#define TIRQ3	ITCN_BASE + 0x13
#define TISR0	ITCN_BASE + 0x18
#define TISR1	ITCN_BASE + 0x19
#define TISR2	ITCN_BASE + 0x1a
#define TISR3	ITCN_BASE + 0x1b
#define TCSR	ITCN_BASE + 0x1c


/* Analog-to-Digital Converter (ADC) */

#define ADCA_BASE	0x1280

#define ADCA_ADCR1		ADCA_BASE + 0x0
#define ADCA_ADCR2		ADCA_BASE + 0x1
#define ADCA_ADZCC		ADCA_BASE + 0x2
#define ADCA_ADLST1		ADCA_BASE + 0x3
#define ADCA_ADLST2		ADCA_BASE + 0x4
#define ADCA_ADSDIS		ADCA_BASE + 0x5
#define ADCA_ADSTAT		ADCA_BASE + 0x6
#define ADCA_ADLSTAT	ADCA_BASE + 0x7
#define ADCA_ADZCSTAT	ADCA_BASE + 0x8
#define ADCA_ADRSLT0	ADCA_BASE + 0x9
#define ADCA_ADRSLT1	ADCA_BASE + 0xa
#define ADCA_ADRSLT2	ADCA_BASE + 0xb
#define ADCA_ADRSLT3	ADCA_BASE + 0xc
#define ADCA_ADRSLT4	ADCA_BASE + 0xd
#define ADCA_ADRSLT5	ADCA_BASE + 0xe
#define ADCA_ADRSLT6	ADCA_BASE + 0xf
#define ADCA_ADRSLT7	ADCA_BASE + 0x10
#define ADCA_ADDLLMT0	ADCA_BASE + 0x11
#define ADCA_ADDLLMT1	ADCA_BASE + 0x12
#define ADCA_ADDLLMT2	ADCA_BASE + 0x13
#define ADCA_ADDLLMT3	ADCA_BASE + 0x14
#define ADCA_ADDLLMT4	ADCA_BASE + 0x15
#define ADCA_ADDLLMT5	ADCA_BASE + 0x16
#define ADCA_ADDLLMT6	ADCA_BASE + 0x17
#define ADCA_ADDLLMT7	ADCA_BASE + 0x18
#define ADCA_ADHLMT0	ADCA_BASE + 0x19
#define ADCA_ADHLMT1	ADCA_BASE + 0x1a
#define ADCA_ADHLMT2	ADCA_BASE + 0x1b
#define ADCA_ADHLMT3	ADCA_BASE + 0x1c
#define ADCA_ADHLMT4	ADCA_BASE + 0x1d
#define ADCA_ADHLMT5	ADCA_BASE + 0x1e
#define ADCA_ADHLMT6	ADCA_BASE + 0x1f
#define ADCA_ADHLMT7	ADCA_BASE + 0x20
#define ADCA_ADOFS0		ADCA_BASE + 0x21
#define ADCA_ADOFS1		ADCA_BASE + 0x22
#define ADCA_ADOFS2		ADCA_BASE + 0x23
#define ADCA_ADOFS3		ADCA_BASE + 0x24
#define ADCA_ADOFS4		ADCA_BASE + 0x25
#define ADCA_ADOFS5		ADCA_BASE + 0x26
#define ADCA_ADOFS6		ADCA_BASE + 0x27
#define ADCA_ADOFS7		ADCA_BASE + 0x28

#define ADCB_BASE	0x12c0

#define ADCB_ADCR1		ADCB_BASE + 0x0
#define ADCB_ADCR2		ADCB_BASE + 0x1
#define ADCB_ADZCC		ADCB_BASE + 0x2
#define ADCB_ADLST1		ADCB_BASE + 0x3
#define ADCB_ADLST2		ADCB_BASE + 0x4
#define ADCB_ADSDIS		ADCB_BASE + 0x5
#define ADCB_ADSTAT		ADCB_BASE + 0x6
#define ADCB_ADLSTAT	ADCB_BASE + 0x7
#define ADCB_ADZCSTAT	ADCB_BASE + 0x8
#define ADCB_ADRSLT0	ADCB_BASE + 0x9
#define ADCB_ADRSLT1	ADCB_BASE + 0xa
#define ADCB_ADRSLT2	ADCB_BASE + 0xb
#define ADCB_ADRSLT3	ADCB_BASE + 0xc
#define ADCB_ADRSLT4	ADCB_BASE + 0xd
#define ADCB_ADRSLT5	ADCB_BASE + 0xe
#define ADCB_ADRSLT6	ADCB_BASE + 0xf
#define ADCB_ADRSLT7	ADCB_BASE + 0x10
#define ADCB_ADDLLMT0	ADCB_BASE + 0x11
#define ADCB_ADDLLMT1	ADCB_BASE + 0x12
#define ADCB_ADDLLMT2	ADCB_BASE + 0x13
#define ADCB_ADDLLMT3	ADCB_BASE + 0x14
#define ADCB_ADDLLMT4	ADCB_BASE + 0x15
#define ADCB_ADDLLMT5	ADCB_BASE + 0x16
#define ADCB_ADDLLMT6	ADCB_BASE + 0x17
#define ADCB_ADDLLMT7	ADCB_BASE + 0x18
#define ADCB_ADHLMT0	ADCB_BASE + 0x19
#define ADCB_ADHLMT1	ADCB_BASE + 0x1a
#define ADCB_ADHLMT2	ADCB_BASE + 0x1b
#define ADCB_ADHLMT3	ADCB_BASE + 0x1c
#define ADCB_ADHLMT4	ADCB_BASE + 0x1d
#define ADCB_ADHLMT5	ADCB_BASE + 0x1e
#define ADCB_ADHLMT6	ADCB_BASE + 0x1f
#define ADCB_ADHLMT7	ADCB_BASE + 0x20
#define ADCB_ADOFS0		ADCB_BASE + 0x21
#define ADCB_ADOFS1		ADCB_BASE + 0x22
#define ADCB_ADOFS2		ADCB_BASE + 0x23
#define ADCB_ADOFS3		ADCB_BASE + 0x24
#define ADCB_ADOFS4		ADCB_BASE + 0x25
#define ADCB_ADOFS5		ADCB_BASE + 0x26
#define ADCB_ADOFS6		ADCB_BASE + 0x27
#define ADCB_ADOFS7		ADCB_BASE + 0x28


/* Serial Coummunications Interface (SCI) */
#define SCI0_BASE	0x1300

#define SCI0_SCIBR	SCI0_BASE + 0
#define SCI0_SCICR	SCI0_BASE + 1
#define SCI0_SCISR	SCI0_BASE + 2
#define SCI0_SCIDR	SCI0_BASE + 3

#define SCI1_BASE	0x1310

#define SCI1_SCIBR	SCI1_BASE + 0
#define SCI1_SCICR	SCI1_BASE + 1
#define SCI1_SCISR	SCI1_BASE + 2
#define SCI1_SCIDR	SCI1_BASE + 3


/* Serial Peripheral Interface (SPI) */
#define SPI_BASE	0x1320

#define SPSCR	SPI_BASE + 0
#define SPDSR	SPI_BASE + 1
#define SPDRR	SPI_BASE + 2
#define SPDTR	SPI_BASE + 3


/* Computer Operating Properly */
#define COP_BASE	0x1330

#define COPCTL	COP_BASE + 0
#define COPTO	COP_BASE + 1
#define COPSRV	COP_BASE + 2


/* Program Flash Interface Unit (PFIU) */
#define PFIU_BASE		0x1340

#define PFIU_CNTL		PFIU_BASE + 0x0
#define PFIU_PE			PFIU_BASE + 0x1
#define PFIU_EE			PFIU_BASE + 0x2
#define PFIU_ADDR		PFIU_BASE + 0x3
#define PFIU_DATA		PFIU_BASE + 0x4
#define PFIU_IE			PFIU_BASE + 0x5
#define PFIU_IS			PFIU_BASE + 0x6
#define PFIU_IP			PFIU_BASE + 0x7
#define PFIU_CKDVISOR	PFIU_BASE + 0x8
#define PFIU_TERASEL	PFIU_BASE + 0x9
#define PFIU_TMEL		PFIU_BASE + 0xa
#define PFIU_TNVSL		PFIU_BASE + 0xb
#define PFIU_TPGSL		PFIU_BASE + 0xc
#define PFIU_TPROGL		PFIU_BASE + 0xd
#define PFIU_TVHL		PFIU_BASE + 0xe
#define PFIU_TVH1L		PFIU_BASE + 0xf
#define PFIU_TRCVL		PFIU_BASE + 0x10

/* Data Flash Interface Unit (DFIU) */
#define DFIU_BASE		0x1360

#define DFIU_CNTL		DFIU_BASE + 0x0
#define DFIU_PE			DFIU_BASE + 0x1
#define DFIU_EE			DFIU_BASE + 0x2
#define DFIU_ADDR		DFIU_BASE + 0x3
#define DFIU_DATA		DFIU_BASE + 0x4
#define DFIU_IE			DFIU_BASE + 0x5
#define DFIU_IS			DFIU_BASE + 0x6
#define DFIU_IP			DFIU_BASE + 0x7
#define DFIU_CKDVISOR	DFIU_BASE + 0x8
#define DFIU_TERASEL	DFIU_BASE + 0x9
#define DFIU_TMEL		DFIU_BASE + 0xa
#define DFIU_TNVSL		DFIU_BASE + 0xb
#define DFIU_TPGSL		DFIU_BASE + 0xc
#define DFIU_TPROGL		DFIU_BASE + 0xd
#define DFIU_TVHL		DFIU_BASE + 0xe
#define DFIU_TVH1L		DFIU_BASE + 0xf
#define DFIU_TRCVL		DFIU_BASE + 0x10


/* Boot Flash Interface Unit (BFIU) */
#define BFIU_BASE		0x1380

#define BFIU_CNTL		BFIU_BASE + 0x0
#define BFIU_PE			BFIU_BASE + 0x1
#define BFIU_EE			BFIU_BASE + 0x2
#define BFIU_ADDR		BFIU_BASE + 0x3
#define BFIU_DATA		BFIU_BASE + 0x4
#define BFIU_IE			BFIU_BASE + 0x5
#define BFIU_IS			BFIU_BASE + 0x6
#define BFIU_IP			BFIU_BASE + 0x7
#define BFIU_CKDVISOR	BFIU_BASE + 0x8
#define BFIU_TERASEL	BFIU_BASE + 0x9
#define BFIU_TMEL		BFIU_BASE + 0xa
#define BFIU_TNVSL		BFIU_BASE + 0xb
#define BFIU_TPGSL		BFIU_BASE + 0xc
#define BFIU_TPROGL		BFIU_BASE + 0xd
#define BFIU_TVHL		BFIU_BASE + 0xe
#define BFIU_TVH1L		BFIU_BASE + 0xf
#define BFIU_TRCVL		BFIU_BASE + 0x10


/* Clock Generation */
#define CLKGEN_BASE	0x13a0

#define PLLCR		CLKGEN_BASE + 0
#define PLLDB		CLKGEN_BASE + 1
#define PLLSR		CLKGEN_BASE + 2
#define TESTR		CLKGEN_BASE + 3
#define CLKOSR		CLKGEN_BASE + 4
#define ISOCTL		CLKGEN_BASE + 5


/* General Purpose Input/Output (GPIO) */

#define GPIOA_BASE		0x13b0

#define GPIO_A_PUR		GPIOA_BASE + 0x0
#define GPIO_A_DR		GPIOA_BASE + 0x1
#define GPIO_A_DDR		GPIOA_BASE + 0x2
#define GPIO_A_PER		GPIOA_BASE + 0x3
#define GPIO_A_IAR		GPIOA_BASE + 0x4
#define GPIO_A_IENR		GPIOA_BASE + 0x5
#define GPIO_A_IPOLR	GPIOA_BASE + 0x6
#define GPIO_A_IPR		GPIOA_BASE + 0x7
#define GPIO_A_IESR		GPIOA_BASE + 0x8

////+++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
#define GPIOB_BASE		0x13c0

#define GPIO_B_PUR		GPIOB_BASE + 0x0
#define GPIO_B_DR		GPIOB_BASE + 0x1
#define GPIO_B_DDR		GPIOB_BASE + 0x2

#define GPIO_B_PER		GPIOB_BASE + 0x3  /////////

#define GPIO_B_IAR		GPIOB_BASE + 0x4
#define GPIO_B_IENR		GPIOB_BASE + 0x5
#define GPIO_B_IPOLR	GPIOB_BASE + 0x6
#define GPIO_B_IPR		GPIOB_BASE + 0x7
#define GPIO_B_IESR		GPIOB_BASE + 0x8
////++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++

#define GPIOD_BASE		0x13e0

#define GPIO_D_PUR		GPIOD_BASE + 0x0
#define GPIO_D_DR		GPIOD_BASE + 0x1
#define GPIO_D_DDR		GPIOD_BASE + 0x2
#define GPIO_D_PER		GPIOD_BASE + 0x3
#define GPIO_D_IAR		GPIOD_BASE + 0x4
#define GPIO_D_IENR		GPIOD_BASE + 0x5
#define GPIO_D_IPOLR	GPIOD_BASE + 0x6
#define GPIO_D_IPR		GPIOD_BASE + 0x7
#define GPIO_D_IESR		GPIOD_BASE + 0x8


#define GPIOE_BASE		0x13f0

#define GPIO_E_PUR		GPIOE_BASE + 0x0
#define GPIO_E_DR		GPIOE_BASE + 0x1
#define GPIO_E_DDR		GPIOE_BASE + 0x2
#define GPIO_E_PER		GPIOE_BASE + 0x3
#define GPIO_E_IAR		GPIOE_BASE + 0x4
#define GPIO_E_IENR		GPIOE_BASE + 0x5
#define GPIO_E_IPOLR	GPIOE_BASE + 0x6
#define GPIO_E_IPR		GPIOE_BASE + 0x7
#define GPIO_E_IESR		GPIOE_BASE + 0x8


#endif /* _56807_H */