📄 dsp56f807.h
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/* metrowerks sample code */
#ifndef _56807_H
#define _56807_H
/* On-Chip Core Configuration Registers */
#define OPGDBR 0xffff
#define IPR 0xfffb //////Interrupt Priority Register (IPR)///////////
#define BCR 0xfff9
/* System Integration Module (SIM) */
#define SYS_BASE 0x1000
#define SYS_CTRL SYS_BASE + 0x0
#define SYS_STS SYS_BASE + 0x1
#define MSH_ID SYS_BASE + 0x6
#define LSH_ID SYS_BASE + 0x7
#define TST_REG0 SYS_BASE + 0x18
#define TST_REG1 SYS_BASE + 0x19
#define TST_REG2 SYS_BASE + 0x1a
#define TST_REG3 SYS_BASE + 0x1b
#define TST_REG4 SYS_BASE + 0x1c
/* Program Flash Interface Unit (PFIU2) */
#define PFIU2_BASE 0x1420
#define PFIU2_CNTL PFIU2_BASE + 0x0
#define PFIU2_PE PFIU2_BASE + 0x1
#define PFIU2_EE PFIU2_BASE + 0x2
#define PFIU2_ADDR PFIU2_BASE + 0x3
#define PFIU2_DATA PFIU2_BASE + 0x4
#define PFIU2_IE PFIU2_BASE + 0x5
#define PFIU2_IS PFIU2_BASE + 0x6
#define PFIU2_IP PFIU2_BASE + 0x7
#define PFIU2_CKDVISOR PFIU2_BASE + 0x8
#define PFIU2_TERASEL PFIU2_BASE + 0x9
#define PFIU2_TMEL PFIU2_BASE + 0xa
#define PFIU2_TNVSL PFIU2_BASE + 0xb
#define PFIU2_TPGSL PFIU2_BASE + 0xc
#define PFIU2_TPROGL PFIU2_BASE + 0xd
#define PFIU2_TVHL PFIU2_BASE + 0xe
#define PFIU2_TVH1L PFIU2_BASE + 0xf
#define PFIU2_TRCVL PFIU2_BASE + 0x10
/* Quad timer */
#define TMRA_BASE 0x1100
#define TMRA0_CMP1 TMRA_BASE + 0x0
#define TMRA0_CMP2 TMRA_BASE + 0x1
#define TMRA0_CAP TMRA_BASE + 0x2
#define TMRA0_LOAD TMRA_BASE + 0x3
#define TMRA0_HOLD TMRA_BASE + 0x4
#define TMRA0_CNTR TMRA_BASE + 0x5
#define TMRA0_CTRL TMRA_BASE + 0x6
#define TMRA0_SCR TMRA_BASE + 0x7
#define TMRA1_CMP1 TMRA_BASE + 0x8
#define TMRA1_CMP2 TMRA_BASE + 0x9
#define TMRA1_CAP TMRA_BASE + 0xa
#define TMRA1_LOAD TMRA_BASE + 0xb
#define TMRA1_HOLD TMRA_BASE + 0xc
#define TMRA1_CNTR TMRA_BASE + 0xd
#define TMRA1_CTRL TMRA_BASE + 0xe
#define TMRA1_SCR TMRA_BASE + 0xf
#define TMRA2_CMP1 TMRA_BASE + 0x10
#define TMRA2_CMP2 TMRA_BASE + 0x11
#define TMRA2_CAP TMRA_BASE + 0x12
#define TMRA2_LOAD TMRA_BASE + 0x13
#define TMRA2_HOLD TMRA_BASE + 0x14
#define TMRA2_CNTR TMRA_BASE + 0x15
#define TMRA2_CTRL TMRA_BASE + 0x16
#define TMRA2_SCR TMRA_BASE + 0x17
#define TMRA3_CMP1 TMRA_BASE + 0x18
#define TMRA3_CMP2 TMRA_BASE + 0x19
#define TMRA3_CAP TMRA_BASE + 0x1a
#define TMRA3_LOAD TMRA_BASE + 0x1b
#define TMRA3_HOLD TMRA_BASE + 0x1c
#define TMRA3_CNTR TMRA_BASE + 0x1d
#define TMRA3_CTRL TMRA_BASE + 0x1e
#define TMRA3_SCR TMRA_BASE + 0x1f
#define TMRB_BASE 0x1120
#define TMRB0_CMP1 TMRB_BASE + 0x0
#define TMRB0_CMP2 TMRB_BASE + 0x1
#define TMRB0_CAP TMRB_BASE + 0x2
#define TMRB0_LOAD TMRB_BASE + 0x3
#define TMRB0_HOLD TMRB_BASE + 0x4
#define TMRB0_CNTR TMRB_BASE + 0x5
#define TMRB0_CTRL TMRB_BASE + 0x6
#define TMRB0_SCR TMRB_BASE + 0x7
#define TMRB1_CMP1 TMRB_BASE + 0x8
#define TMRB1_CMP2 TMRB_BASE + 0x9
#define TMRB1_CAP TMRB_BASE + 0xa
#define TMRB1_LOAD TMRB_BASE + 0xb
#define TMRB1_HOLD TMRB_BASE + 0xc
#define TMRB1_CNTR TMRB_BASE + 0xd
#define TMRB1_CTRL TMRB_BASE + 0xe
#define TMRB1_SCR TMRB_BASE + 0xf
#define TMRB2_CMP1 TMRB_BASE + 0x10
#define TMRB2_CMP2 TMRB_BASE + 0x11
#define TMRB2_CAP TMRB_BASE + 0x12
#define TMRB2_LOAD TMRB_BASE + 0x13
#define TMRB2_HOLD TMRB_BASE + 0x14
#define TMRB2_CNTR TMRB_BASE + 0x15
#define TMRB2_CTRL TMRB_BASE + 0x16
#define TMRB2_SCR TMRB_BASE + 0x17
#define TMRB3_CMP1 TMRB_BASE + 0x18
#define TMRB3_CMP2 TMRB_BASE + 0x19
#define TMRB3_CAP TMRB_BASE + 0x1a
#define TMRB3_LOAD TMRB_BASE + 0x1b
#define TMRB3_HOLD TMRB_BASE + 0x1c
#define TMRB3_CNTR TMRB_BASE + 0x1d
#define TMRB3_CTRL TMRB_BASE + 0x1e
#define TMRB3_SCR TMRB_BASE + 0x1f
#define TMRC_BASE 0x1140
#define TMRC0_CMP1 TMRC_BASE + 0x0
#define TMRC0_CMP2 TMRC_BASE + 0x1
#define TMRC0_CAP TMRC_BASE + 0x2
#define TMRC0_LOAD TMRC_BASE + 0x3
#define TMRC0_HOLD TMRC_BASE + 0x4
#define TMRC0_CNTR TMRC_BASE + 0x5
#define TMRC0_CTRL TMRC_BASE + 0x6
#define TMRC0_SCR TMRC_BASE + 0x7
#define TMRC1_CMP1 TMRC_BASE + 0x8
#define TMRC1_CMP2 TMRC_BASE + 0x9
#define TMRC1_CAP TMRC_BASE + 0xa
#define TMRC1_LOAD TMRC_BASE + 0xb
#define TMRC1_HOLD TMRC_BASE + 0xc
#define TMRC1_CNTR TMRC_BASE + 0xd
#define TMRC1_CTRL TMRC_BASE + 0xe
#define TMRC1_SCR TMRC_BASE + 0xf
#define TMRC2_CMP1 TMRC_BASE + 0x10
#define TMRC2_CMP2 TMRC_BASE + 0x11
#define TMRC2_CAP TMRC_BASE + 0x12
#define TMRC2_LOAD TMRC_BASE + 0x13
#define TMRC2_HOLD TMRC_BASE + 0x14
#define TMRC2_CNTR TMRC_BASE + 0x15
#define TMRC2_CTRL TMRC_BASE + 0x16
#define TMRC2_SCR TMRC_BASE + 0x17
#define TMRC3_CMP1 TMRC_BASE + 0x18
#define TMRC3_CMP2 TMRC_BASE + 0x19
#define TMRC3_CAP TMRC_BASE + 0x1a
#define TMRC3_LOAD TMRC_BASE + 0x1b
#define TMRC3_HOLD TMRC_BASE + 0x1c
#define TMRC3_CNTR TMRC_BASE + 0x1d
#define TMRC3_CTRL TMRC_BASE + 0x1e
#define TMRC3_SCR TMRC_BASE + 0x1f
#define TMRD_BASE 0x1160
#define TMRD0_CMP1 TMRD_BASE + 0x0
#define TMRD0_CMP2 TMRD_BASE + 0x1
#define TMRD0_CAP TMRD_BASE + 0x2
#define TMRD0_LOAD TMRD_BASE + 0x3
#define TMRD0_HOLD TMRD_BASE + 0x4
#define TMRD0_CNTR TMRD_BASE + 0x5
#define TMRD0_CTRL TMRD_BASE + 0x6
#define TMRD0_SCR TMRD_BASE + 0x7
#define TMRD1_CMP1 TMRD_BASE + 0x8
#define TMRD1_CMP2 TMRD_BASE + 0x9
#define TMRD1_CAP TMRD_BASE + 0xa
#define TMRD1_LOAD TMRD_BASE + 0xb
#define TMRD1_HOLD TMRD_BASE + 0xc
#define TMRD1_CNTR TMRD_BASE + 0xd
#define TMRD1_CTRL TMRD_BASE + 0xe
#define TMRD1_SCR TMRD_BASE + 0xf
#define TMRD2_CMP1 TMRD_BASE + 0x10
#define TMRD2_CMP2 TMRD_BASE + 0x11
#define TMRD2_CAP TMRD_BASE + 0x12
#define TMRD2_LOAD TMRD_BASE + 0x13
#define TMRD2_HOLD TMRD_BASE + 0x14
#define TMRD2_CNTR TMRD_BASE + 0x15
#define TMRD2_CTRL TMRD_BASE + 0x16
#define TMRD2_SCR TMRD_BASE + 0x17
#define TMRD3_CMP1 TMRD_BASE + 0x18
#define TMRD3_CMP2 TMRD_BASE + 0x19
#define TMRD3_CAP TMRD_BASE + 0x1a
#define TMRD3_LOAD TMRD_BASE + 0x1b
#define TMRD3_HOLD TMRD_BASE + 0x1c
#define TMRD3_CNTR TMRD_BASE + 0x1d
#define TMRD3_CTRL TMRD_BASE + 0x1e
#define TMRD3_SCR TMRD_BASE + 0x1f
/* Controller Area Network (CAN) */
#define CAN_BASE 0x1180
#define CANCTL0 CAN_BASE + 0x0
#define CANCTL1 CAN_BASE + 0x1
#define CANBTR0 CAN_BASE + 0x2
#define CANBR1 CAN_BASE + 0x3
#define CANRFLG CAN_BASE + 0x4
#define CANRIER CAN_BASE + 0x5
#define CANTFLG CAN_BASE + 0x6
#define CANTCR CAN_BASE + 0x7
#define CANIDAC CAN_BASE + 0x8
#define CANRXERR CAN_BASE + 0xe
#define CANTXERR CAN_BASE + 0xf
#define CANIDAR0 CAN_BASE + 0x10
#define CANIDAR1 CAN_BASE + 0x11
#define CANIDAR2 CAN_BASE + 0x12
#define CANIDAR3 CAN_BASE + 0x13
#define CANIDAR4 CAN_BASE + 0x18
#define CANIDAR5 CAN_BASE + 0x19
#define CANIDAR6 CAN_BASE + 0x1a
#define CANIDAR7 CAN_BASE + 0x1b
#define CANIDMR0 CAN_BASE + 0x14
#define CANIDMR1 CAN_BASE + 0x15
#define CANIDMR2 CAN_BASE + 0x16
#define CANIDMR3 CAN_BASE + 0x17
#define CANIDMR4 CAN_BASE + 0x1c
#define CANIDMR5 CAN_BASE + 0x1d
#define CANIDMR6 CAN_BASE + 0x1e
#define CANIDMR7 CAN_BASE + 0x1f
#define CAN_RB_IDR0 CAN_BASE + 0x40
#define CAN_RB_IDR1 CAN_BASE + 0x41
#define CAN_RB_IDR2 CAN_BASE + 0x42
#define CAN_RB_IDR3 CAN_BASE + 0x43
#define CAN_RB_DSR0 CAN_BASE + 0x44
#define CAN_RB_DSR1 CAN_BASE + 0x45
#define CAN_RB_DSR2 CAN_BASE + 0x46
#define CAN_RB_DSR3 CAN_BASE + 0x47
#define CAN_RB_DSR4 CAN_BASE + 0x48
#define CAN_RB_DSR5 CAN_BASE + 0x49
#define CAN_RB_DSR6 CAN_BASE + 0x4a
#define CAN_RB_DSR7 CAN_BASE + 0x4b
#define CAN_RB_DLR CAN_BASE + 0x4c
#define CAN_RB_TBPR CAN_BASE + 0x4d
#define CAN_TB0_IDR0 CAN_BASE + 0x50
#define CAN_TB0_IDR1 CAN_BASE + 0x51
#define CAN_TB0_IDR2 CAN_BASE + 0x52
#define CAN_TB0_IDR3 CAN_BASE + 0x53
#define CAN_TB0_DSR0 CAN_BASE + 0x54
#define CAN_TB0_DSR1 CAN_BASE + 0x55
#define CAN_TB0_DSR2 CAN_BASE + 0x56
#define CAN_TB0_DSR3 CAN_BASE + 0x57
#define CAN_TB0_DSR4 CAN_BASE + 0x58
#define CAN_TB0_DSR5 CAN_BASE + 0x59
#define CAN_TB0_DSR6 CAN_BASE + 0x5a
#define CAN_TB0_DSR7 CAN_BASE + 0x5b
#define CAN_TB0_DLR CAN_BASE + 0x5c
#define CAN_TB0_TBPR CAN_BASE + 0x5d
#define CAN_TB1_IDR0 CAN_BASE + 0x60
#define CAN_TB1_IDR1 CAN_BASE + 0x61
#define CAN_TB1_IDR2 CAN_BASE + 0x62
#define CAN_TB1_IDR3 CAN_BASE + 0x63
#define CAN_TB1_DSR0 CAN_BASE + 0x64
#define CAN_TB1_DSR1 CAN_BASE + 0x65
#define CAN_TB1_DSR2 CAN_BASE + 0x66
#define CAN_TB1_DSR3 CAN_BASE + 0x67
#define CAN_TB1_DSR4 CAN_BASE + 0x68
#define CAN_TB1_DSR5 CAN_BASE + 0x69
#define CAN_TB1_DSR6 CAN_BASE + 0x6a
#define CAN_TB1_DSR7 CAN_BASE + 0x6b
#define CAN_TB1_DLR CAN_BASE + 0x6c
#define CAN_TB1_TBPR CAN_BASE + 0x6d
#define CAN_TB2_IDR0 CAN_BASE + 0x70
#define CAN_TB2_IDR1 CAN_BASE + 0x71
#define CAN_TB2_IDR2 CAN_BASE + 0x72
#define CAN_TB2_IDR3 CAN_BASE + 0x73
#define CAN_TB2_DSR0 CAN_BASE + 0x74
#define CAN_TB2_DSR1 CAN_BASE + 0x75
#define CAN_TB2_DSR2 CAN_BASE + 0x76
#define CAN_TB2_DSR3 CAN_BASE + 0x77
#define CAN_TB2_DSR4 CAN_BASE + 0x78
#define CAN_TB2_DSR5 CAN_BASE + 0x79
#define CAN_TB2_DSR6 CAN_BASE + 0x7a
#define CAN_TB2_DSR7 CAN_BASE + 0x7b
#define CAN_TB2_DLR CAN_BASE + 0x7c
#define CAN_TB2_TBPR CAN_BASE + 0x7d
/* Pulse Width Modulator Module (PWM) */
#define PWMA_BASE 0x1200
#define PWMA_PMCTL PWMA_BASE + 0x0
#define PWMA_PMFCTL PWMA_BASE + 0x1
#define PWMA_PMFSA PWMA_BASE + 0x2
#define PWMA_PMOUT PWMA_BASE + 0x3
#define PWMA_PMCNT PWMA_BASE + 0x4
#define PWMA_PWMCM PWMA_BASE + 0x5
#define PWMA_PWMVAL0 PWMA_BASE + 0x6
#define PWMA_PWMVAL1 PWMA_BASE + 0x7
#define PWMA_PWMVAL2 PWMA_BASE + 0x8
#define PWMA_PWMVAL3 PWMA_BASE + 0x9
#define PWMA_PWMVAL4 PWMA_BASE + 0xa
#define PWMA_PWMVAL5 PWMA_BASE + 0xb
#define PWMA_PMDEADTM PWMA_BASE + 0xc
#define PWMA_PMDISMAP1 PWMA_BASE + 0xd
#define PWMA_PMDISMAP2 PWMA_BASE + 0xe
#define PWMA_PMDCFG PWMA_BASE + 0xf
#define PWMA_PMCCR PWMA_BASE + 0x10
#define PWMA_PMPORT PWMA_BASE + 0x11
#define PWMB_BASE 0x1220
#define PWMB_PMCTL PWMB_BASE + 0x0
#define PWMB_PMFCTL PWMB_BASE + 0x1
#define PWMB_PMFSA PWMB_BASE + 0x2
#define PWMB_PMOUT PWMB_BASE + 0x3
#define PWMB_PMCNT PWMB_BASE + 0x4
#define PWMB_PWMCM PWMB_BASE + 0x5
#define PWMB_PWMVAL0 PWMB_BASE + 0x6
#define PWMB_PWMVAL1 PWMB_BASE + 0x7
#define PWMB_PWMVAL2 PWMB_BASE + 0x8
#define PWMB_PWMVAL3 PWMB_BASE + 0x9
#define PWMB_PWMVAL4 PWMB_BASE + 0xa
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