f243_c.h

电机无速度传感器矢量控制在ＤＳＰ２４０７下的实现程序

#define MBX3B		(volatile unsigned int *)0x721D	
#define MBX3C		(volatile unsigned int *)0x721E	
#define MBX3D		(volatile unsigned int *)0x721F	
#define MSGID4L		(volatile unsigned int *)0x7220	
#define MSGID4H		(volatile unsigned int *)0x7221	
#define MSGCTRL4	(volatile unsigned int *)0x7222	
#define MBX4A		(volatile unsigned int *)0x7224	
#define MBX4B		(volatile unsigned int *)0x7225	
#define MBX4C		(volatile unsigned int *)0x7226	
#define MBX4D		(volatile unsigned int *)0x7227	
#define MSGID5L		(volatile unsigned int *)0x7228	
#define MSGID5H		(volatile unsigned int *)0x7229	
#define MSGCTRL5	(volatile unsigned int *)0x722A	
#define MBX5A		(volatile unsigned int *)0x722C	
#define MBX5B		(volatile unsigned int *)0x722D	
#define MBX5C		(volatile unsigned int *)0x722E	
#define MBX5D		(volatile unsigned int *)0x722F	
#define MDER		(volatile unsigned int *)0x7100	
#define TCR			(volatile unsigned int *)0x7101	
#define RCR			(volatile unsigned int *)0x7102	
#define MCR			(volatile unsigned int *)0x7103
#define BCR2		(volatile unsigned int *)0x7104	
#define BCR1		(volatile unsigned int *)0x7105	
#define ESR			(volatile unsigned int *)0x7106	
#define GSR			(volatile unsigned int *)0x7107	
#define CEC			(volatile unsigned int *)0x7108	
#define CAN_IFR		(volatile unsigned int *)0x7109	
#define CAN_IMR		(volatile unsigned int *)0x710A	
#define LAM0_H		(volatile unsigned int *)0x710B	
#define LAM0_L		(volatile unsigned int *)0x710C	
#define LAM1_H		(volatile unsigned int *)0x710D	
#define LAM1_L		(volatile unsigned int *)0x710E	
#define MSGID0L		(volatile unsigned int *)0x7200		
#define MSGID0H		(volatile unsigned int *)0x7201		
#define MSGCTRL0	(volatile unsigned int *)0x7202		
#define MBX0A		(volatile unsigned int *)0x7204	
#define MBX0B		(volatile unsigned int *)0x7205	
#define MBX0C		(volatile unsigned int *)0x7206		
#define MBX0D		(volatile unsigned int *)0x7207	
#define MSGID1L		(volatile unsigned int *)0x7208		
#define MSGID1H		(volatile unsigned int *)0x7209	
#define MSGCTRL1	(volatile unsigned int *)0x720A	
#define MBX1A		(volatile unsigned int *)0x720C		
#define MBX1B		(volatile unsigned int *)0x720D	
#define MBX1C		(volatile unsigned int *)0x720E		
#define MBX1D		(volatile unsigned int *)0x720F		
#define MSGID2L		(volatile unsigned int *)0x7210	
#define MSGID2H		(volatile unsigned int *)0x7211		
#define MSGCTRL2	(volatile unsigned int *)0x7212		
#define MBX2A		(volatile unsigned int *)0x7214		
#define MBX2B		(volatile unsigned int *)0x7215	
#define MBX2C		(volatile unsigned int *)0x7216		
#define MBX2D		(volatile unsigned int *)0x7217	
#define MSGID3L		(volatile unsigned int *)0x7218	
#define MSGID3H		(volatile unsigned int *)0x7219		
#define MSGCTRL3	(volatile unsigned int *)0x721A	
#define MBX3A		(volatile unsigned int *)0x721C	
#define MBX3B		(volatile unsigned int *)0x721D	
#define MBX3C		(volatile unsigned int *)0x721E	
#define MBX3D		(volatile unsigned int *)0x721F		
#define MSGID4L		(volatile unsigned int *)0x7220	
#define MSGID4H		(volatile unsigned int *)0x7221	
#define MSGCTRL4	(volatile unsigned int *)0x7222	
#define MBX4A		(volatile unsigned int *)0x7224		
#define MBX4B		(volatile unsigned int *)0x7225		
#define MBX4C		(volatile unsigned int *)0x7226		
#define MBX4D		(volatile unsigned int *)0x7227		
#define MSGID5L		(volatile unsigned int *)0x7228		
#define MSGID5H		(volatile unsigned int *)0x7229		
#define MSGCTRL5	(volatile unsigned int *)0x722A	
#define MBX5A		(volatile unsigned int *)0x722C		
#define MBX5B		(volatile unsigned int *)0x722D		
#define MBX5C		(volatile unsigned int *)0x722E		
#define MBX5D		(volatile unsigned int *)0x722F		

/*
;External Interrupt Registers
;~~~~~~~~~~~~~~~~~~~~~~~~~~~~
XINT1		.set	07070h		;Interrupt 1 Control Register
XINT2 	.set	07071h		;Interrupt 2 Control Register
*/
#define	XINT1	 (volatile unsigned int *)0x7070
#define	XINT2	 (volatile unsigned int *)0x7071

/*
;Digital I/O
;~~~~~~~~~~~
OCRA		.set	07090h		;Output Control Reg A
OCRB		.set	07092h		;Output Control Reg B
PADATDIR	.set	07098h		;I/O port A Data & Direction reg.
PBDATDIR	.set	0709Ah		;I/O port B Data & Direction reg.
PCDATDIR	.set	0709Ch		;I/O port C Data & Direction reg.
PDDATDIR	.set	0709Ch		;I/O port D Data & Direction reg.
*/
#define	OCRA		(volatile unsigned int *)0x7090
#define	OCRB		(volatile unsigned int *)0x7092
#define	PADATDIR	(volatile unsigned int *)0x7098
#define	PBDATDIR	(volatile unsigned int *)0x709A
#define	PCDATDIR	(volatile unsigned int *)0x709C
#define	PDDATDIR	(volatile unsigned int *)0x709E


/*
;General Purpose Timer Registers - Event Manager (EV)
;~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
GPTCON		.set	7400h			;General Purpose Timer Control Register	
T1CNT		.set	7401h			;GP Timer 1 Counter Register
T1CMPR		.set	7402h			;GP Timer 1 Compare Register
T1PR		.set	7403h			;GP Timer 1 Period Register
T1CON		.set	7404h			;GP Timer 1 Control Register
T2CNT		.set	7405h			;GP Timer 2 Counter Register
T2CMPR		.set	7406h			;GP Timer 2 Compare Register
T2PR		.set	7407h			;GP Timer 2 Period Register
T2CON		.set	7408h			;GP Timer 2 Control Register
*/
#define	GPTCON	(volatile unsigned int *)0x7400
#define	T1CNT	(volatile unsigned int *)0x7401
#define	T1CMPR	(volatile unsigned int *)0x7402
#define	T1PR	(volatile unsigned int *)0x7403
#define	T1CON	(volatile unsigned int *)0x7404
#define	T2CNT	(volatile unsigned int *)0x7405
#define	T2CMPR	(volatile unsigned int *)0x7406
#define	T2PR	(volatile unsigned int *)0x7407
#define	T2CON	(volatile unsigned int *)0x7408

/*
;Full & Simple Compare Unit Registers - Event Manager (EV)
;~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
COMCON		.set	7411h			;Compare Control Register
ACTR		.set	7413h			;Full Compare Action Control Register
DBTCON		.set	7415h			;Dead-band Timer Control Register
CMPR1		.set	7417h			;Full Compare Unit 1 Compare Register
CMPR2		.set	7418h			;Full Compare Unit 2 Compare Register
CMPR3		.set	7419h			;Full Compare Unit 3 Compare Register
*/
#define	COMCON	(volatile unsigned int *)0x7411
#define	ACTR	(volatile unsigned int *)0x7413
#define	DBTCON	(volatile unsigned int *)0x7415
#define	CMPR1	(volatile unsigned int *)0x7417
#define	CMPR2	(volatile unsigned int *)0x7418
#define	CMPR3	(volatile unsigned int *)0x7419
/*
;Capture & QEP Registers - Event Manager (EV)
;~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
CAPCON		.set	7420h			;Capture Control Register
CAPFIFO		.set	7422h			;Capture FIFO Status Register
CAP1FIFO	.set	7423h			;Capture 1 Two-level deep FIFO Register
CAP2FIFO	.set	7424h			;Capture 2 Two-level deep FIFO Register
CAP3FIFO	.set	7425h			;Capture 3 Two-level deep FIFO Register
*/
#define CAPCON		(volatile unsigned int *)0x7420
#define CAPFIFO		(volatile unsigned int *)0x7422
#define CAP1FIFO	(volatile unsigned int *)0x7423
#define CAP2FIFO	(volatile unsigned int *)0x7424
#define CAP3FIFO	(volatile unsigned int *)0x7425
 
/*
;Interrupt Registers - Event Manager (EV)
;~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
EVIMRA	.set	742Ch			;EV Interrupt Mask Register A
EVIMRB	.set	742Dh			;EV Interrupt Mask Register B
EVIMRC	.set	742Eh			;EV Interrupt Mask Register C
EVIFRA	.set	742Fh			;EV Interrupt Flag Register A
EVIFRB	.set	7430h			;EV Interrupt Flag Register B
EVIFRC	.set	7431h			;EV Interrupt Flag Register C
EVIVRA	.set	7432h			;EV Interrupt Vector Register A
*/
#define	EVIMRA	(volatile unsigned int *)0x742C
#define	EVIMRB	(volatile unsigned int *)0x742D
#define	EVIMRC	(volatile unsigned int *)0x742E
#define	EVIFRA	(volatile unsigned int *)0x742F
#define	EVIFRB	(volatile unsigned int *)0x7430
#define	EVIFRC	(volatile unsigned int *)0x7431

/*
;Flash Module Registers (mapped into Program space!!!!!!!!!!!!!!!)
;~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
SEG_CTR		.set	0h			;Flash Segment Control Register
WADRS		.set	2h			;Flash Write Address Register
WDATA		.set	3h			;Flash Write Data Register
*/

/*
;Wait State Generator Registers (mapped into I/O space!!!!!!!!!!!!!)
;~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
WSGR		.set	0FFFFh		;Wait State Generator Register
*/
#define	WSGR	portffff
ioport unsigned portffff; /*should THE LINE be inserted into .c file???*/

/*
;-----------------------------------------------------------------------
; Constant Definitions
;-----------------------------------------------------------------------

;Data Memory Boundary Addresses
;~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
B0_SADDR	.set	00200h		;Block B0 start address
B0_EADDR	.set	002FFh		;Block B0 end address
B1_SADDR	.set	00300h		;Block B1 start address
B1_EADDR	.set	003FFh		;Block B1 end address
B2_SADDR	.set	00060h		;Block B2 start address
B2_EADDR	.set	0007Fh		;Block B2 end address
XDATA_SADDR	.set	08000h		;External Data Space start address
XDATA_EADDR	.set  	09FFFh		;External Data Space end address

;Bit codes for Test Bit instruction (BIT)
;~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
BIT15		.set	0000h		;Bit Code for 15
BIT14		.set	0001h		;Bit Code for 14
BIT13		.set	0002h		;Bit Code for 13
BIT12		.set	0003h		;Bit Code for 12
BIT11		.set	0004h		;Bit Code for 11
BIT10		.set	0005h		;Bit Code for 10
BIT9		.set	0006h		;Bit Code for 9
BIT8		.set	0007h		;Bit Code for 8
BIT7		.set	0008h		;Bit Code for 7
BIT6		.set	0009h		;Bit Code for 6
BIT5		.set	000Ah		;Bit Code for 5
BIT4		.set	000Bh		;Bit Code for 4
BIT3		.set	000Ch		;Bit Code for 3
BIT2		.set	000Dh		;Bit Code for 2
BIT1		.set	000Eh		;Bit Code for 1
BIT0		.set	000Fh		;Bit Code for 0

;Bit masks used by the SBIT0 & SBIT1 Macros
;~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
B15_MSK 	.set	8000h		;Bit Mask for 15
B14_MSK 	.set	4000h		;Bit Mask for 14
B13_MSK 	.set	2000h		;Bit Mask for 13
B12_MSK 	.set	1000h		;Bit Mask for 12
B11_MSK 	.set	0800h		;Bit Mask for 11
B10_MSK 	.set	0400h		;Bit Mask for 10
B9_MSK	.set	0200h		;Bit Mask for 9
B8_MSK	.set	0100h		;Bit Mask for 8
B7_MSK	.set	0080h		;Bit Mask for 7
B6_MSK	.set	0040h		;Bit Mask for 6
B5_MSK	.set	0020h		;Bit Mask for 5
B4_MSK	.set	0010h		;Bit Mask for 4
B3_MSK	.set	0008h		;Bit Mask for 3
B2_MSK	.set	0004h		;Bit Mask for 2
B1_MSK	.set	0002h		;Bit Mask for 1
B0_MSK	.set	0001h		;Bit Mask for 0

;-----------------------------------------------------------------------
; M A C R O - Definitions
;-----------------------------------------------------------------------

SBIT0		.macro	DMA, MASK		;Clear bit Macro
		LACC	DMA				
		AND	#(0FFFFh-MASK)		
		SACL	DMA				
		.endm

SBIT1		.macro	DMA, MASK		;Set bit Macro
		LACC	DMA
		OR	#(MASK)
		SACL	DMA
		.endm

KICK_DOG	.macro				;Watchdog reset macro
		LDP	#00E0h			;DP-->7000h-707Fh
		SPLK	#05555h, WDKEY		;WDCNTR is enabled to be reset by next AAh
		SPLK	#0AAAAh, WDKEY		;WDCNTR is reset
		LDP	#0h				;DP-->0000h-007Fh
		.endm

*/