pulse.h

基于DSP2407产生带死区的6个PWM脉冲的源代码！

/*****************************************************************************/
/* File name:     Pulse.h                                                    */
/* Last modified: 2005.5.23                                                  */
/* Description:   Head file of pulse. Varables and I/O definitions of 2407   */
/* Copy Right:    Guoguo                                                     */
/*****************************************************************************/

#include	"Reg_2407_C.h"

unsigned int i;

/************************************************/
/*  Define board port resorce                   */
/************************************************/
/*;NAME           PORT ADDRESS  COMMENTs

DAC1    .set    0000h  ;Board DAC1 port address (I/O space)
DAC2    .set    0001h  ;Board DAC2 port address (I/O space)
DAC3    .set    0002h  ;Board DAC3 port address (I/O space)
DAC4    .set    0003h  ;Board DAC4 port address (I/O space)
DAC_EN  .set    0004h  ;Board DAC enable port address(I/O space)
OUT_EN  .set    0005h  ;output opt adress  
SWITCH  .set    0006h  ;switch address 
LED     .set    0007h  ;Output data to LED

/***********************************************************/
/* The followings define DATA_IN, DATA_OUT in dualport ram */
/***********************************************************/ 
/*DATA_OUT1 .set  8000h ; output address parameters to dual-port ram->First start ADC Results
DATA_OUT2 .set  8010h ; output address parameters to dual-port ram->Second start ADC Results
DATA_OUT3 .set  8020h ; output address parameters to dual-port ram->Third start ADC Results
DATA_IN  .set  8400h ; input address parameters from dual-port ram
   
cmp1_d1  .set  8400h ;CMP1 value memory address in dual-port ram 
cmp2_d2  .set  8401h ;CMP2 value memory address in dual-port ram
cmp3_d3  .set  8402h ;CMP3 value memory address in dual-port ram     
 
sensor1  .set  8406h ;Data 1 to be output by DAC1 in Dual-port ram
sensor2  .set  8407h ;Data 2 to be output by DAC2 in Dual-port ram
sensor3  .set  8408h ;Data 3 to be output by DAC3 in Dual-port ram
sensor4  .set  8409h ;Data 4 to be output by DAC4 in Dual-port ram

cap_value    .set 8060h ;new capture value at 16xCLK_in
captureflag  .set 8061h ;capture happends flag    

temp_out   .set 8200h
temp_in    .set 8420h


DRAMF_R .set 8fffh ; right port(2407) mail box of dual port ram
DRAMF_L .set 8ffeh ; left port(vc33)mail box of dual port ram

T1s .set 1500   ; Timer 1 period  counting-up/down mode  750=50uS  1500=100uS switch  period
T2s .set 0ff00h ; Timer 2 period  counting-up mode
T3s .set 1500   ; Timer 3 period  counting-up/down mode  750=50uS  1500=100uS control period
T4s .set 0ff00h ; Timer 4 period

Vdc_max .set  7480h ;7480h=500v 2e80h=200V 1280h=80V
 

 
/*--------------Subroutine for Initializing CPU Core-------------------------*/
/* Initialized Registers:                                                    */
/*    IFR, IMR, SCSR1, SCSR2, XINT1CR, XINT2CR, WDCR, WSGR                   */ 
/*---------------------------------------------------------------------------*/

void CPU_Init(void)
{
    asm(" SETC INTM ");		/*DISABLE INTERRUPTS                             */
    asm(" CLRC SXM ");		/*SUPPRESSES SIGN EXTENSION                      */
    asm(" CLRC OVM ");		/*RESET OVERFLOW MODE                            */
    asm(" CLRC CNF ");		/*CONFIG BLOCK B0 TO DATA MEM                    */
    *IFR=0xFFFF;			/*CLEAR ALL INTERRUPT FLAGS                      */
    *IMR=0x000A;			/*ENABLE INTERRUPTS: INT4 CAP 0x00001000B        */  
    
    *SCSR1=0x020D;
/*
  0000001011111101B
  ||||||||||||||||
  FEDCBA9876543210
  bit 0:	ILLADR, Illegal address detect bit
  bit 1:	Reserved
  bit 2:	EVA CLKEN, enable EVA clock
  bit 3:	EVB CLKEN, enable EVB clock
  bit 4:	CAN CLKEN, disable CAN clock
  bit 5:	SPI CLKEN, disable SPI clock
  bit 6:	SCI CLKEN, disable SCI clock
  bit 7:	ADC CLKEN, disable ADC clock
  bit 8:	REserved
  bit 11-9:	PLL Clock prescale select. 2*Fin
  bit 13-12:	LPM(1:0), low power mode--IDLE1(LPM0)
  bit 14:	CLKSRC, CLKOUT pin has CPU clock
  bit 15:	Reserved
*/ 
                        
  *SCSR2=0x000E;    
/*
  0000000000001110B
  ||||||||||||||||
  FEDCBA9876543210
  bit 1-0:	SARAM program/data space select, mapped internally to Data space
  bit 2:	MP/MC, Microprocessor mode(Jtag)/Microcontroller mode
  bit 3:	Boot Enable, disabled
  bit 4:	external memory interface signals in normal driven mode
  bit 5:	Watch dog override, allow user to disable WD
  bit 6:	Input Qualifier Clocks, Input Qualifier circuitry blocks
  		    glitches up to 5 clock cycles long
  bit 15-7:	Reserved
*/
    *XINT1CR=0x08001;
/*
  1000000000000001
  ||||||||||||||||
  FEDCBA9876543210
  bit 0:	XINT1 Enable, enable xint1
  bit 1:	XINT1 Priority, High priority
  bit 2:	XINT1 Polarity, falling edge(high to low transition)
  bit 14-3:	Reserved
  bit 15:	XINT1 flag
*/
    *XINT2CR=0x08001;        /*same as XINT1CR                               */
    *WDCR=0x006F;  			 /*DISABLE WD IF VCCP=5V (JP5 IN POS. 2-3)       */
    WSGR=0x0000;             /*SET WAIT STATE GENERAT                        */
}	   
/*---------------------------------------------------------------------------*/

/*-----------------------Subroutine for Initializing IO Port-----------------*/  
/* Initialized Registers:                                                    */
/*    MCRA, MCRB, MCRC,                                                      */
/*    PADATDIR, PBDATDIR, PCDATDIR, PDDATDIR, PEDATDIR, PFDATDIR             */ 
/*---------------------------------------------------------------------------*/
void IOport_Init(void)
{
    *MCRA=0x103F;	
/*
IOPA0..7 are set as SCITXD, SCIRXD, XINT1, CAP1/QEP1, CAP2/QEP2, CAP3, IOPA6, IOPA7
IOPB0..7 are set as IOPB0, IOPB1, IOPB2, IOPB3, T1PWM/T1CMP, IOPB5, IOPB6, IOPB7
*/
    *MCRB=0x0FFFF;
/*
IOPC0..7 are set as W/R, BIO, SPISIMO, SPISOMI, SPICLK, SPISTE, CANTX, CANRX
IOPD0..7 are set as XINT2/ADCSOC, EMU0, EMU1, TCK, TDI, TDO, TMS, TMS2
*/
    *MCRC=0x0FFE;
/* 
IOPE0..7 are set as IOPE0, PWM7, PWM8, PWM9, PWM10, PWM11, PWM12, CAP4/QEP3
IOPF0..7 are set as CAP5/QEP4, CAP6, T3PWM/T3CMP, T4PWM/T4CMP, IOPF4, IOPF5, Reserved, Reserved
*/
    *PADATDIR=0x0C0C0;
/*
Because IOPA0..7 are set as primary function, this register has no effect.
Except of IOPA6 and IOPA7.
*/
    *PBDATDIR=0x0FF00;
/*
Set IOPB0..7 as output and corresponding I/O pin low.
*/
    *PCDATDIR=0x0000;
/*
Because IOPC0..7 are set as primary function, this register has no effect.
*/
    *PDDATDIR=0x0000;
/*
Because IOPD0..7 are set as primary function, this register has no effect.
*/     
    *PEDATDIR=0x0100;
/*
Set IOPE0 as output and corresponding I/O pin low
*/
    *PFDATDIR=0x3000;
/* 
Set IOPF4 and IOPF5 as output and corresponding I/O pins low.
*/
}
/*---------------------------------------------------------------------------*/

/*--------------------Subroutine for Initializing EV module------------------*/
/*Initialized Registers:                                                     */
/*    T1CON, T2CON, T3CON, T4CON, GPTCONA, GPTCONB, COMCONA, COMCONB,        */
/*    ACTRA, ACTRB, DBTCONA, DBTCONB, CAPCONA, CAPCONB                       */
/*    EVAIFRA, EVAIMRA, EVAIFRB, EVAIMRB, EVAIFRC, EVAIMRC                   */
/*    EVBIFRA, EVBIMRA, EVBIFRB, EVBIMRB, EVBIFRC, EVBIMRC                   */
/*    T1PR, T2PR, T3PR, T4PR, T1CMPR, T2CMPR, T3CMPR, T4CMPR                 */
/*    CMPR1, CMPR2, CMPR3, CMPR4, CMPR5, CMPR6                               */
/*---------------------------------------------------------------------------*/
void EV_Init(void)
{
    *T1CON=0x1404;	/* continuous-up mode, X/16, reload when counter=0 or PR value */
    *T2CON=0x1404;
    *T3CON=0x0802;  /* disable T3 and T4 */
    *T4CON=0x0802;
/*
bit 15-14:    free, soft
bit 13:       Reserved
bit 12-11:    Continuous up/ count mode
bit 10-8:     input clock prescalser, =cpu clock/1
bit 7:        Timer1.3 use own TENABLE bit, Timer2.4 use TENABLE bit of 1 or 3
bit 6:        Disable timer operations
bit 5-4:      timer1.3 use internal source, timer2.4 use QEP circuit    
bit 3-2:      timer compare register reload when counter is 0
bit 1:        enable timer compare operation
bit 0:        use own period register
*/
    *GPTCONA=0x0000;
    *GPTCONB=0x0000;
/*
no event start ADC, disable all timer compare output
set compare output forced low.
*/
    *COMCONA=0x0200;  
    *COMCONB=0x0200;
/*
bit 15:        Disable compare operation
bit 14-13:     CMPRx reload when T1CNT or T3CNT=0
bit 12:        Space vector PWM enable
bit 11-10:     ACTR reload when T1CNT OR T3CNT=0
bit 9:         Full compare output enable
bit 8:         PDPINT status
bit 7-0:       Reserved
*/
    *ACTRA=0x0666;
    *ACTRB=0x0666;
/*
Space vector rotation direction positive
Space vector set as 0
CMP1..6 are set as active 1high-2low-3high-4low-5high-6low
*/
    *DBTCONA=0x0000;	/* disable all deadtime control */ 
    *DBTCONB=0x0000;
/*
bit 15-12:    Reserved
bit 11-8:     DBT3-0 set as F
bit 7-5:      Enable all compare unit
bit 4-2:      Prescaler set as 000B, deadtime is 8 us on 30MHz device.
bit 1-0:      Reserved
*/
    *CAPCONA=0x9004;
    *CAPCONB=0x0000;
/*
Disable CAP1,2,4,5,6. Enable CAP 3.
Select GP Timer2 as clock source, Detect rising edge
*/
    *EVAIFRA=0x0FFFF;                  
    *EVAIMRA=0x0080;        
/*bit 10,     9,      8,     7,     3,      2,      1,      0
      T1OFINT,T1UFINT,T1CINT,T1PINT,CMP3INT,CMP2INT,CMP1INT,PDPINTA      
  oterh bit: reserved
*/  
    *EVAIFRB=0x000F;
    *EVAIMRB=0x0000;
/*bit 3,      2,      1,     0
      T2OFINT,T2UFINT,T2CINT,T2PINT
  other bit: reserved
*/
    *EVAIFRC=0x0007;
    *EVAIMRC=0x0004;
/*bit 2,      1,      0
      CAP3INT,CAP2INT,CAP1INT 
  other bit: reserved
*/
    
    *EVBIFRA=0x0FFFF;
    *EVBIMRA=0x0000;  
/*bit 10,     9,      8,     7,     3,      2,      1,      0
      T3OFINT,T3UFINT,T3CINT,T3PINT,CMP6INT,CMP5INT,CMP4INT,PDPINTB      
  oterh bit: reserved
*/    
    *EVBIFRB=0x000F;
    *EVBIMRB=0x0000;
/*bit 3,      2,      1,     0
      T4OFINT,T4UFINT,T4CINT,T4PINT
  other bit: reserved
*/    
    *EVBIFRC=0x0007;
    *EVBIMRC=0x0000;  
/*bit 2,      1,      0
      CAP6INT,CAP5INT,CAP4INT 
  other bit: reserved
*/
/*
Clear all EV module interrupt flage   
Enable Timer1 underflow interrupt     

*/
    *T1PR=0x0018;	/* 0x0019=25, 40/3us */
    *T1CNT=0;
    *T2PR=0x0FFFF;   
    *T2CNT=0;
    *CMPR1=0;
    *CMPR2=0;
    *CMPR3=0;
    *CMPR4=0;
    *CMPR5=0;
    *CMPR6=0;
}
/*---------------------------------------------------------------------------*/