📄 pic16f1516.h
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// EUSART Transmit Interrupt Flag bit
volatile bit TXIF @ ((unsigned)&PIR1*8)+4;
// EUSART Receive Interrupt Flag bit
volatile bit RCIF @ ((unsigned)&PIR1*8)+5;
// A/D Converter Interrupt Flag bit
volatile bit ADIF @ ((unsigned)&PIR1*8)+6;
// Timer1 Gate Interrupt Flag bit
volatile bit TMR1GIF @ ((unsigned)&PIR1*8)+7;
#ifndef _LIB_BUILD
volatile union {
struct {
unsigned TMR1IF : 1;
unsigned TMR2IF : 1;
unsigned CCP1IF : 1;
unsigned SSPIF : 1;
unsigned TXIF : 1;
unsigned RCIF : 1;
unsigned ADIF : 1;
unsigned TMR1GIF : 1;
};
} PIR1bits @ 0x011;
#endif
// Register: PIR2
volatile unsigned char PIR2 @ 0x012;
// bit and bitfield definitions
volatile bit CCP2IF @ ((unsigned)&PIR2*8)+0;
volatile bit BCLIF @ ((unsigned)&PIR2*8)+3;
volatile bit OSFIF @ ((unsigned)&PIR2*8)+7;
#ifndef _LIB_BUILD
volatile union {
struct {
unsigned CCP2IF : 1;
unsigned : 1;
unsigned : 1;
unsigned BCLIF : 1;
unsigned : 1;
unsigned : 1;
unsigned : 1;
unsigned OSFIF : 1;
};
} PIR2bits @ 0x012;
#endif
// Register: TMR0
volatile unsigned char TMR0 @ 0x015;
// bit and bitfield definitions
// bit and bitfield definitions
// Register: TMR1L
volatile unsigned char TMR1L @ 0x016;
// bit and bitfield definitions
// Register: TMR1H
volatile unsigned char TMR1H @ 0x017;
// bit and bitfield definitions
// Register: TMR1
volatile unsigned int TMR1 @ 0x016;
// Register: T1CON
volatile unsigned char T1CON @ 0x018;
// bit and bitfield definitions
volatile bit TMR1ON @ ((unsigned)&T1CON*8)+0;
volatile bit nT1SYNC @ ((unsigned)&T1CON*8)+2;
volatile bit T1OSCEN @ ((unsigned)&T1CON*8)+3;
volatile bit T1CKPS0 @ ((unsigned)&T1CON*8)+4;
volatile bit T1CKPS1 @ ((unsigned)&T1CON*8)+5;
volatile bit TMR1CS0 @ ((unsigned)&T1CON*8)+6;
volatile bit TMR1CS1 @ ((unsigned)&T1CON*8)+7;
#ifndef _LIB_BUILD
volatile union {
struct {
unsigned TMR1ON : 1;
unsigned : 1;
unsigned nT1SYNC : 1;
unsigned T1OSCEN : 1;
unsigned T1CKPS0 : 1;
unsigned T1CKPS1 : 1;
unsigned TMR1CS0 : 1;
unsigned TMR1CS1 : 1;
};
struct {
unsigned : 4;
unsigned T1CKPS : 2;
unsigned TMR1CS : 2;
};
} T1CONbits @ 0x018;
#endif
// Register: T1GCON
volatile unsigned char T1GCON @ 0x019;
// bit and bitfield definitions
volatile bit T1GSS0 @ ((unsigned)&T1GCON*8)+0;
volatile bit T1GSS1 @ ((unsigned)&T1GCON*8)+1;
volatile bit T1GVAL @ ((unsigned)&T1GCON*8)+2;
volatile bit T1GGO_nDONE @ ((unsigned)&T1GCON*8)+3;
volatile bit T1GSPM @ ((unsigned)&T1GCON*8)+4;
volatile bit T1GTM @ ((unsigned)&T1GCON*8)+5;
volatile bit T1GPOL @ ((unsigned)&T1GCON*8)+6;
volatile bit TMR1GE @ ((unsigned)&T1GCON*8)+7;
#ifndef _LIB_BUILD
volatile union {
struct {
unsigned T1GSS0 : 1;
unsigned T1GSS1 : 1;
unsigned T1GVAL : 1;
unsigned T1GGO_nDONE : 1;
unsigned T1GSPM : 1;
unsigned T1GTM : 1;
unsigned T1GPOL : 1;
unsigned TMR1GE : 1;
};
struct {
unsigned T1GSS : 2;
};
} T1GCONbits @ 0x019;
#endif
// Register: TMR2
volatile unsigned char TMR2 @ 0x01A;
// bit and bitfield definitions
// Register: PR2
volatile unsigned char PR2 @ 0x01B;
// bit and bitfield definitions
// Register: T2CON
volatile unsigned char T2CON @ 0x01C;
// bit and bitfield definitions
volatile bit T2CKPS0 @ ((unsigned)&T2CON*8)+0;
volatile bit T2CKPS1 @ ((unsigned)&T2CON*8)+1;
volatile bit TMR2ON @ ((unsigned)&T2CON*8)+2;
volatile bit T2OUTPS0 @ ((unsigned)&T2CON*8)+3;
volatile bit T2OUTPS1 @ ((unsigned)&T2CON*8)+4;
volatile bit T2OUTPS2 @ ((unsigned)&T2CON*8)+5;
volatile bit T2OUTPS3 @ ((unsigned)&T2CON*8)+6;
#ifndef _LIB_BUILD
volatile union {
struct {
unsigned T2CKPS0 : 1;
unsigned T2CKPS1 : 1;
unsigned TMR2ON : 1;
unsigned T2OUTPS0 : 1;
unsigned T2OUTPS1 : 1;
unsigned T2OUTPS2 : 1;
unsigned T2OUTPS3 : 1;
};
struct {
unsigned T2CKPS : 2;
unsigned : 1;
unsigned T2OUTPS : 4;
};
} T2CONbits @ 0x01C;
#endif
//
// Special function register definitions: Bank 1
//
// Register: TRISA
// PORTA Data Direction Control Register
volatile unsigned char TRISA @ 0x08C;
// bit and bitfield definitions
volatile bit TRISA0 @ ((unsigned)&TRISA*8)+0;
volatile bit TRISA1 @ ((unsigned)&TRISA*8)+1;
volatile bit TRISA2 @ ((unsigned)&TRISA*8)+2;
volatile bit TRISA3 @ ((unsigned)&TRISA*8)+3;
volatile bit TRISA4 @ ((unsigned)&TRISA*8)+4;
volatile bit TRISA5 @ ((unsigned)&TRISA*8)+5;
volatile bit TRISA6 @ ((unsigned)&TRISA*8)+6;
volatile bit TRISA7 @ ((unsigned)&TRISA*8)+7;
#ifndef _LIB_BUILD
volatile union {
struct {
unsigned TRISA0 : 1;
unsigned TRISA1 : 1;
unsigned TRISA2 : 1;
unsigned TRISA3 : 1;
unsigned TRISA4 : 1;
unsigned TRISA5 : 1;
unsigned TRISA6 : 1;
unsigned TRISA7 : 1;
};
} TRISAbits @ 0x08C;
#endif
// Register: TRISB
// PORTB Data Direction Control Register
volatile unsigned char TRISB @ 0x08D;
// bit and bitfield definitions
volatile bit TRISB0 @ ((unsigned)&TRISB*8)+0;
volatile bit TRISB1 @ ((unsigned)&TRISB*8)+1;
volatile bit TRISB2 @ ((unsigned)&TRISB*8)+2;
volatile bit TRISB3 @ ((unsigned)&TRISB*8)+3;
volatile bit TRISB4 @ ((unsigned)&TRISB*8)+4;
volatile bit TRISB5 @ ((unsigned)&TRISB*8)+5;
volatile bit TRISB6 @ ((unsigned)&TRISB*8)+6;
volatile bit TRISB7 @ ((unsigned)&TRISB*8)+7;
#ifndef _LIB_BUILD
volatile union {
struct {
unsigned TRISB0 : 1;
unsigned TRISB1 : 1;
unsigned TRISB2 : 1;
unsigned TRISB3 : 1;
unsigned TRISB4 : 1;
unsigned TRISB5 : 1;
unsigned TRISB6 : 1;
unsigned TRISB7 : 1;
};
} TRISBbits @ 0x08D;
#endif
// Register: TRISC
// PORTC Data Direction Control Register
volatile unsigned char TRISC @ 0x08E;
// bit and bitfield definitions
volatile bit TRISC0 @ ((unsigned)&TRISC*8)+0;
volatile bit TRISC1 @ ((unsigned)&TRISC*8)+1;
volatile bit TRISC2 @ ((unsigned)&TRISC*8)+2;
volatile bit TRISC3 @ ((unsigned)&TRISC*8)+3;
volatile bit TRISC4 @ ((unsigned)&TRISC*8)+4;
volatile bit TRISC5 @ ((unsigned)&TRISC*8)+5;
volatile bit TRISC6 @ ((unsigned)&TRISC*8)+6;
volatile bit TRISC7 @ ((unsigned)&TRISC*8)+7;
#ifndef _LIB_BUILD
volatile union {
struct {
unsigned TRISC0 : 1;
unsigned TRISC1 : 1;
unsigned TRISC2 : 1;
unsigned TRISC3 : 1;
unsigned TRISC4 : 1;
unsigned TRISC5 : 1;
unsigned TRISC6 : 1;
unsigned TRISC7 : 1;
};
} TRISCbits @ 0x08E;
#endif
// Register: TRISE
volatile unsigned char TRISE @ 0x090;
// bit and bitfield definitions
// Register: PIE1
// Peripheral Interrupt Enable Register 1
volatile unsigned char PIE1 @ 0x091;
// bit and bitfield definitions
// TMR1 Overflow Interrupt Enable bit
volatile bit TMR1IE @ ((unsigned)&PIE1*8)+0;
// TMR2 to PR2 Match Interrupt Enable bit
volatile bit TMR2IE @ ((unsigned)&PIE1*8)+1;
// CCP1 Interrupt Enable bit
volatile bit CCP1IE @ ((unsigned)&PIE1*8)+2;
// Master Synchronous Serial Port (MSSP) Interrupt Enable bit
volatile bit SSPIE @ ((unsigned)&PIE1*8)+3;
// EUSART Transmit Interrupt Enable bit
volatile bit TXIE @ ((unsigned)&PIE1*8)+4;
// EUSART Receive Interrupt Enable bit
volatile bit RCIE @ ((unsigned)&PIE1*8)+5;
// A/D Converter Interrupt Enable bit
volatile bit ADIE @ ((unsigned)&PIE1*8)+6;
// Timer1 Gate Interrupt Enable bit
volatile bit TMR1GIE @ ((unsigned)&PIE1*8)+7;
#ifndef _LIB_BUILD
volatile union {
struct {
unsigned TMR1IE : 1;
unsigned TMR2IE : 1;
unsigned CCP1IE : 1;
unsigned SSPIE : 1;
unsigned TXIE : 1;
unsigned RCIE : 1;
unsigned ADIE : 1;
unsigned TMR1GIE : 1;
};
} PIE1bits @ 0x091;
#endif
// Register: PIE2
// Peripheral Interrupt Enable Register 2
volatile unsigned char PIE2 @ 0x092;
// bit and bitfield definitions
// CCP2 Interrupt Enable bit
volatile bit CCP2IE @ ((unsigned)&PIE2*8)+0;
// MSSP Bus Collision Interrupt Interrupt Enable bit
volatile bit BCLIE @ ((unsigned)&PIE2*8)+3;
// CCP2 Interrupt Enable bit
volatile bit OSFIE @ ((unsigned)&PIE2*8)+7;
#ifndef _LIB_BUILD
volatile union {
struct {
unsigned CCP2IE : 1;
unsigned : 1;
unsigned : 1;
unsigned BCLIE : 1;
unsigned : 1;
unsigned : 1;
unsigned : 1;
unsigned OSFIE : 1;
};
} PIE2bits @ 0x092;
#endif
// Register: OPTION_REG
// Option Register
volatile unsigned char OPTION_REG @ 0x095;
// bit and bitfield definitions
// Prescaler Rate Select bits
volatile bit PS0 @ ((unsigned)&OPTION_REG*8)+0;
// Prescaler Rate Select bits
volatile bit PS1 @ ((unsigned)&OPTION_REG*8)+1;
// Prescaler Rate Select bits
volatile bit PS2 @ ((unsigned)&OPTION_REG*8)+2;
// Prescaler Active bit
volatile bit PSA @ ((unsigned)&OPTION_REG*8)+3;
// TMR0 Source Edge Select bit
volatile bit TMR0SE @ ((unsigned)&OPTION_REG*8)+4;
// TMR0 Clock Source Select bit
volatile bit TMR0CS @ ((unsigned)&OPTION_REG*8)+5;
// Interrupt Edge Select bit
volatile bit INTEDG @ ((unsigned)&OPTION_REG*8)+6;
// Weak Pull-up Enable bit
volatile bit nWPUEN @ ((unsigned)&OPTION_REG*8)+7;
volatile bit T0SE @ ((unsigned)&OPTION_REG*8)+4;
volatile bit T0CS @ ((unsigned)&OPTION_REG*8)+5;
#ifndef _LIB_BUILD
volatile union {
struct {
unsigned PS0 : 1;
unsigned PS1 : 1;
unsigned PS2 : 1;
unsigned PSA : 1;
unsigned TMR0SE : 1;
unsigned TMR0CS : 1;
unsigned INTEDG : 1;
unsigned nWPUEN : 1;
};
struct {
unsigned PS : 3;
unsigned : 1;
unsigned T0SE : 1;
unsigned T0CS : 1;
};
} OPTION_REGbits @ 0x095;
#endif
// Register: PCON
// Power Control Register
volatile unsigned char PCON @ 0x096;
// bit and bitfield definitions
// Brown-out Reset Status bit
volatile bit nBOR @ ((unsigned)&PCON*8)+0;
// Power-on Reset Status bit
volatile bit nPOR @ ((unsigned)&PCON*8)+1;
// RESET Instruction Flag bit
volatile bit nRI @ ((unsigned)&PCON*8)+2;
// MCLR Reset Flag bit
volatile bit nRMCLR @ ((unsigned)&PCON*8)+3;
volatile bit nRWDT @ ((unsigned)&PCON*8)+4;
// Stack Underflow Flag bit
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