📄 pic16f767.h
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//
// Register Declarations for Microchip 16F767 Processor
//
//
// This header file was automatically generated by:
//
// inc2h.pl V1.6
//
// Copyright (c) 2002, Kevin L. Pauba, All Rights Reserved
//
// SDCC is licensed under the GNU Public license (GPL) v2. Note that
// this license covers the code to the compiler and other executables,
// but explicitly does not cover any code or objects generated by sdcc.
// We have not yet decided on a license for the run time libraries, but
// it will not put any requirements on code linked against it. See:
//
// http://www.gnu.org/copyleft/gpl/html
//
// See http://sdcc.sourceforge.net/ for the latest information on sdcc.
//
//
#ifndef P16F767_H
#define P16F767_H
//
// Register addresses.
//
#define INDF_ADDR 0x0000
#define TMR0_ADDR 0x0001
#define PCL_ADDR 0x0002
#define STATUS_ADDR 0x0003
#define FSR_ADDR 0x0004
#define PORTA_ADDR 0x0005
#define PORTB_ADDR 0x0006
#define PORTC_ADDR 0x0007
#define PORTE_ADDR 0x0009
#define PCLATH_ADDR 0x000A
#define INTCON_ADDR 0x000B
#define PIR1_ADDR 0x000C
#define PIR2_ADDR 0x000D
#define TMR1L_ADDR 0x000E
#define TMR1H_ADDR 0x000F
#define T1CON_ADDR 0x0010
#define TMR2_ADDR 0x0011
#define T2CON_ADDR 0x0012
#define SSPBUF_ADDR 0x0013
#define SSPCON_ADDR 0x0014
#define CCPR1L_ADDR 0x0015
#define CCPR1H_ADDR 0x0016
#define CCP1CON_ADDR 0x0017
#define RCSTA_ADDR 0x0018
#define TXREG_ADDR 0x0019
#define RCREG_ADDR 0x001A
#define CCPR2L_ADDR 0x001B
#define CCPR2H_ADDR 0x001C
#define CCP2CON_ADDR 0x001D
#define ADRESH_ADDR 0x001E
#define ADCON0_ADDR 0x001F
#define OPTION_REG_ADDR 0x0081
#define TRISA_ADDR 0x0085
#define TRISB_ADDR 0x0086
#define TRISC_ADDR 0x0087
#define TRISE_ADDR 0x0089
#define PIE1_ADDR 0x008C
#define PIE2_ADDR 0x008D
#define PCON_ADDR 0x008E
#define OSCCON_ADDR 0x008F
#define OSCTUNE_ADDR 0x0090
#define SSPCON2_ADDR 0x0091
#define PR2_ADDR 0x0092
#define SSPADD_ADDR 0x0093
#define SSPSTAT_ADDR 0x0094
#define CCPR3L_ADDR 0x0095
#define CCPR3H_ADDR 0x0096
#define CCP3CON_ADDR 0x0097
#define TXSTA_ADDR 0x0098
#define SPBRG_ADDR 0x0099
#define ADCON2_ADDR 0x009B
#define CMCON_ADDR 0x009C
#define CVRCON_ADDR 0x009D
#define ADRESL_ADDR 0x009E
#define ADCON1_ADDR 0x009F
#define WDTCON_ADDR 0x0105
#define LVDCON_ADDR 0x0109
#define PMDATA_ADDR 0x010C
#define PMADR_ADDR 0x010D
#define PMDATH_ADDR 0x010E
#define PMADRH_ADDR 0x010F
#define PMCON1_ADDR 0x018C
//
// Memory organization.
//
#pragma memmap INDF_ADDR INDF_ADDR SFR 0x000 // INDF
#pragma memmap TMR0_ADDR TMR0_ADDR SFR 0x000 // TMR0
#pragma memmap PCL_ADDR PCL_ADDR SFR 0x000 // PCL
#pragma memmap STATUS_ADDR STATUS_ADDR SFR 0x000 // STATUS
#pragma memmap FSR_ADDR FSR_ADDR SFR 0x000 // FSR
#pragma memmap PORTA_ADDR PORTA_ADDR SFR 0x000 // PORTA
#pragma memmap PORTB_ADDR PORTB_ADDR SFR 0x000 // PORTB
#pragma memmap PORTC_ADDR PORTC_ADDR SFR 0x000 // PORTC
#pragma memmap PORTE_ADDR PORTE_ADDR SFR 0x000 // PORTE
#pragma memmap PCLATH_ADDR PCLATH_ADDR SFR 0x000 // PCLATH
#pragma memmap INTCON_ADDR INTCON_ADDR SFR 0x000 // INTCON
#pragma memmap PIR1_ADDR PIR1_ADDR SFR 0x000 // PIR1
#pragma memmap PIR2_ADDR PIR2_ADDR SFR 0x000 // PIR2
#pragma memmap TMR1L_ADDR TMR1L_ADDR SFR 0x000 // TMR1L
#pragma memmap TMR1H_ADDR TMR1H_ADDR SFR 0x000 // TMR1H
#pragma memmap T1CON_ADDR T1CON_ADDR SFR 0x000 // T1CON
#pragma memmap TMR2_ADDR TMR2_ADDR SFR 0x000 // TMR2
#pragma memmap T2CON_ADDR T2CON_ADDR SFR 0x000 // T2CON
#pragma memmap SSPBUF_ADDR SSPBUF_ADDR SFR 0x000 // SSPBUF
#pragma memmap SSPCON_ADDR SSPCON_ADDR SFR 0x000 // SSPCON
#pragma memmap CCPR1L_ADDR CCPR1L_ADDR SFR 0x000 // CCPR1L
#pragma memmap CCPR1H_ADDR CCPR1H_ADDR SFR 0x000 // CCPR1H
#pragma memmap CCP1CON_ADDR CCP1CON_ADDR SFR 0x000 // CCP1CON
#pragma memmap RCSTA_ADDR RCSTA_ADDR SFR 0x000 // RCSTA
#pragma memmap TXREG_ADDR TXREG_ADDR SFR 0x000 // TXREG
#pragma memmap RCREG_ADDR RCREG_ADDR SFR 0x000 // RCREG
#pragma memmap CCPR2L_ADDR CCPR2L_ADDR SFR 0x000 // CCPR2L
#pragma memmap CCPR2H_ADDR CCPR2H_ADDR SFR 0x000 // CCPR2H
#pragma memmap CCP2CON_ADDR CCP2CON_ADDR SFR 0x000 // CCP2CON
#pragma memmap ADRESH_ADDR ADRESH_ADDR SFR 0x000 // ADRESH
#pragma memmap ADCON0_ADDR ADCON0_ADDR SFR 0x000 // ADCON0
#pragma memmap OPTION_REG_ADDR OPTION_REG_ADDR SFR 0x000 // OPTION_REG
#pragma memmap TRISA_ADDR TRISA_ADDR SFR 0x000 // TRISA
#pragma memmap TRISB_ADDR TRISB_ADDR SFR 0x000 // TRISB
#pragma memmap TRISC_ADDR TRISC_ADDR SFR 0x000 // TRISC
#pragma memmap TRISE_ADDR TRISE_ADDR SFR 0x000 // TRISE
#pragma memmap PIE1_ADDR PIE1_ADDR SFR 0x000 // PIE1
#pragma memmap PIE2_ADDR PIE2_ADDR SFR 0x000 // PIE2
#pragma memmap PCON_ADDR PCON_ADDR SFR 0x000 // PCON
#pragma memmap OSCCON_ADDR OSCCON_ADDR SFR 0x000 // OSCCON
#pragma memmap OSCTUNE_ADDR OSCTUNE_ADDR SFR 0x000 // OSCTUNE
#pragma memmap SSPCON2_ADDR SSPCON2_ADDR SFR 0x000 // SSPCON2
#pragma memmap PR2_ADDR PR2_ADDR SFR 0x000 // PR2
#pragma memmap SSPADD_ADDR SSPADD_ADDR SFR 0x000 // SSPADD
#pragma memmap SSPSTAT_ADDR SSPSTAT_ADDR SFR 0x000 // SSPSTAT
#pragma memmap CCPR3L_ADDR CCPR3L_ADDR SFR 0x000 // CCPR3L
#pragma memmap CCPR3H_ADDR CCPR3H_ADDR SFR 0x000 // CCPR3H
#pragma memmap CCP3CON_ADDR CCP3CON_ADDR SFR 0x000 // CCP3CON
#pragma memmap TXSTA_ADDR TXSTA_ADDR SFR 0x000 // TXSTA
#pragma memmap SPBRG_ADDR SPBRG_ADDR SFR 0x000 // SPBRG
#pragma memmap ADCON2_ADDR ADCON2_ADDR SFR 0x000 // ADCON2
#pragma memmap CMCON_ADDR CMCON_ADDR SFR 0x000 // CMCON
#pragma memmap CVRCON_ADDR CVRCON_ADDR SFR 0x000 // CVRCON
#pragma memmap ADRESL_ADDR ADRESL_ADDR SFR 0x000 // ADRESL
#pragma memmap ADCON1_ADDR ADCON1_ADDR SFR 0x000 // ADCON1
#pragma memmap WDTCON_ADDR WDTCON_ADDR SFR 0x000 // WDTCON
#pragma memmap LVDCON_ADDR LVDCON_ADDR SFR 0x000 // LVDCON
#pragma memmap PMDATA_ADDR PMDATA_ADDR SFR 0x000 // PMDATA
#pragma memmap PMADR_ADDR PMADR_ADDR SFR 0x000 // PMADR
#pragma memmap PMDATH_ADDR PMDATH_ADDR SFR 0x000 // PMDATH
#pragma memmap PMADRH_ADDR PMADRH_ADDR SFR 0x000 // PMADRH
#pragma memmap PMCON1_ADDR PMCON1_ADDR SFR 0x000 // PMCON1
// LIST
// P16F767.INC Standard Header File, Version 1.00 Microchip Technology, Inc.
// NOLIST
// This header file defines configurations, registers, and other useful bits of
// information for the PIC16F767 microcontroller. These names are taken to match
// the data sheets as closely as possible.
// Note that the processor must be selected before this file is
// included. The processor may be selected the following ways:
// 1. Command line switch:
// C:\ MPASM MYFILE.ASM /PIC16F767
// 2. LIST directive in the source file
// LIST P=PIC16F767
// 3. Processor Type entry in the MPASM full-screen interface
//==========================================================================
//
// Revision History
//
//==========================================================================
//Rev: Date: Reason:
//1.00 05/05/03 Initial Release
//1.01 10/21/03 Made changes to Program Memory register names.
//1.02 04/07/04 Added INT0IE & INT0IF bit names.
//==========================================================================
//
// Verify Processor
//
//==========================================================================
// IFNDEF __16F767
// MESSG "Processor-header file mismatch. Verify selected processor."
// ENDIF
//==========================================================================
//
// Register Definitions
//
//==========================================================================
#define W 0x0000
#define F 0x0001
//----- Register Files------------------------------------------------------
extern __data __at (INDF_ADDR) volatile char INDF;
extern __sfr __at (TMR0_ADDR) TMR0;
extern __data __at (PCL_ADDR) volatile char PCL;
extern __sfr __at (STATUS_ADDR) STATUS;
extern __sfr __at (FSR_ADDR) FSR;
extern __sfr __at (PORTA_ADDR) PORTA;
extern __sfr __at (PORTB_ADDR) PORTB;
extern __sfr __at (PORTC_ADDR) PORTC;
extern __sfr __at (PORTE_ADDR) PORTE;
extern __sfr __at (PCLATH_ADDR) PCLATH;
extern __sfr __at (INTCON_ADDR) INTCON;
extern __sfr __at (PIR1_ADDR) PIR1;
extern __sfr __at (PIR2_ADDR) PIR2;
extern __sfr __at (TMR1L_ADDR) TMR1L;
extern __sfr __at (TMR1H_ADDR) TMR1H;
extern __sfr __at (T1CON_ADDR) T1CON;
extern __sfr __at (TMR2_ADDR) TMR2;
extern __sfr __at (T2CON_ADDR) T2CON;
extern __sfr __at (SSPBUF_ADDR) SSPBUF;
extern __sfr __at (SSPCON_ADDR) SSPCON;
extern __sfr __at (CCPR1L_ADDR) CCPR1L;
extern __sfr __at (CCPR1H_ADDR) CCPR1H;
extern __sfr __at (CCP1CON_ADDR) CCP1CON;
extern __sfr __at (RCSTA_ADDR) RCSTA;
extern __sfr __at (TXREG_ADDR) TXREG;
extern __sfr __at (RCREG_ADDR) RCREG;
extern __sfr __at (CCPR2L_ADDR) CCPR2L;
extern __sfr __at (CCPR2H_ADDR) CCPR2H;
extern __sfr __at (CCP2CON_ADDR) CCP2CON;
extern __sfr __at (ADRESH_ADDR) ADRESH;
extern __sfr __at (ADCON0_ADDR) ADCON0;
extern __sfr __at (OPTION_REG_ADDR) OPTION_REG;
extern __sfr __at (TRISA_ADDR) TRISA;
extern __sfr __at (TRISB_ADDR) TRISB;
extern __sfr __at (TRISC_ADDR) TRISC;
extern __sfr __at (TRISE_ADDR) TRISE;
extern __sfr __at (PIE1_ADDR) PIE1;
extern __sfr __at (PIE2_ADDR) PIE2;
extern __sfr __at (PCON_ADDR) PCON;
extern __sfr __at (OSCCON_ADDR) OSCCON;
extern __sfr __at (OSCTUNE_ADDR) OSCTUNE;
extern __sfr __at (SSPCON2_ADDR) SSPCON2;
extern __sfr __at (PR2_ADDR) PR2;
extern __sfr __at (SSPADD_ADDR) SSPADD;
extern __sfr __at (SSPSTAT_ADDR) SSPSTAT;
extern __sfr __at (CCPR3L_ADDR) CCPR3L;
extern __sfr __at (CCPR3H_ADDR) CCPR3H;
extern __sfr __at (CCP3CON_ADDR) CCP3CON;
extern __sfr __at (TXSTA_ADDR) TXSTA;
extern __sfr __at (SPBRG_ADDR) SPBRG;
extern __sfr __at (ADCON2_ADDR) ADCON2;
extern __sfr __at (CMCON_ADDR) CMCON;
extern __sfr __at (CVRCON_ADDR) CVRCON;
extern __sfr __at (ADRESL_ADDR) ADRESL;
extern __sfr __at (ADCON1_ADDR) ADCON1;
extern __sfr __at (WDTCON_ADDR) WDTCON;
extern __sfr __at (LVDCON_ADDR) LVDCON;
extern __sfr __at (PMDATA_ADDR) PMDATA;
extern __sfr __at (PMADR_ADDR) PMADR;
extern __sfr __at (PMDATH_ADDR) PMDATH;
extern __sfr __at (PMADRH_ADDR) PMADRH;
extern __sfr __at (PMCON1_ADDR) PMCON1;
//----- STATUS Bits --------------------------------------------------------
//----- INTCON Bits --------------------------------------------------------
//----- PIR1 Bits ----------------------------------------------------------
//----- PIR2 Bits ----------------------------------------------------------
//----- T1CON Bits ---------------------------------------------------------
//----- T2CON Bits ---------------------------------------------------------
//----- SSPCON Bits --------------------------------------------------------
//----- CCP1CON Bits -------------------------------------------------------
//----- RCSTA Bits ---------------------------------------------------------
//----- CCP2CON Bits -------------------------------------------------------
//----- ADCON0 Bits --------------------------------------------------------
//----- OPTION Bits -----------------------------------------------------
//----- TRISE Bits ---------------------------------------------------------
//----- PIE1 Bits ----------------------------------------------------------
//----- PIE2 Bits ----------------------------------------------------------
//----- PCON Bits ----------------------------------------------------------
//----- OSCCON Bits -------------------------------------------------------
//----- OSCTUNE Bits -------------------------------------------------------
//----- SSPCON2 Bits --------------------------------------------------------
//----- SSPSTAT Bits -------------------------------------------------------
//----- CCP3CON Bits -------------------------------------------------------
//----- TXSTA Bits ---------------------------------------------------------
//----- ADCON2 Bits ---------------------------------------------------------
//----- CMCON Bits ---------------------------------------------------------
//----- CVRCON Bits --------------------------------------------------------
//----- ADCON1 Bits --------------------------------------------------------
//----- WDTCON Bits --------------------------------------------------------
//----- LVDCON Bits --------------------------------------------------------
//----- PMCON1 Bits --------------------------------------------------------
//==========================================================================
//
// RAM Definition
//
//==========================================================================
// __MAXRAM H'1FF'
// __BADRAM H'08'
// __BADRAM H'88', H'9A'
// __BADRAM H'107'-H'108'
// __BADRAM H'185', H'187'-H'189', H'18D'-H'18F'
//==========================================================================
//
// Configuration Bits
//
//==========================================================================
#define _CONFIG1 0x2007
#define _CONFIG2 0x2008
//Configuration Byte 1 Options
#define _CP_ALL 0x1FFF
#define _CP_OFF 0x3FFF
#define _CCP2_RC1 0x3FFF
#define _CCP2_RB3 0x2FFF
#define _DEBUG_OFF 0x3FFF
#define _DEBUG_ON 0x37FF
#define _VBOR_2_0 0x3FFF
#define _VBOR_2_7 0x3F7F
#define _VBOR_4_2 0x3EFF
#define _VBOR_4_5 0x3E7F
#define _BOREN_1 0x3FFF //MUST BE CONFIGURED IN CONJUCTION W/ BORSEN (CONFIG2)
#define _BOREN_0 0x3FBF //MUST BE CONFIGURED IN CONJUCTION W/ BORSEN (CONFIG2)
#define _MCLR_ON 0x3FFF
#define _MCLR_OFF 0x3FDF
#define _PWRTE_OFF 0x3FFF
#define _PWRTE_ON 0x3FF7
#define _WDT_ON 0x3FFF
#define _WDT_OFF 0x3FFB
#define _EXTRC_CLKOUT 0x3FFF
#define _EXTRC_IO 0x3FFE
#define _INTRC_CLKOUT 0x3FFD
#define _INTRC_IO 0x3FFC
#define _EXTCLK 0x3FEF
#define _HS_OSC 0x3FEE
#define _XT_OSC 0x3FED
#define _LP_OSC 0x3FEC
//Configuration Byte 2 Options
#define _BORSEN_1 0x3FFF //MUST BE CONFIGURED IN CONJUCTION W/ BOREN (CONFIG1)
#define _BORSEN_0 0x3FBF //MUST BE CONFIGURED IN CONJUCTION W/ BOREN (CONFIG1)
#define _IESO_ON 0x3FFF
#define _IESO_OFF 0x3FFD
#define _FCMEN_ON 0x3FFF
#define _FCMEN_OFF 0x3FFE
//**** Brown-out Reset configurations **** (Refer to the 16F7x7 Data Sheet for more details)
//BOREN_1 & BORSEN_1 = BOR enabled and always on
//BOREN_1 & BORSEN_0 = BOR enabled during operation and disabled during sleep by hardware
//BOREN_0 & BORSEN_1 = BOR controlled by software bit SBOREN (PCON,2)
//BOREN_0 & BORSEN_0 = BOR disabled
// To use the Configuration Bits, place the following lines in your source code
// in the following format, and change the configuration value to the desired
// setting (such as CP_OFF to CP_ALL). These are currently commented out here
// and each __CONFIG line should have the preceding semicolon removed when
// pasted into your source code.
//Program Configuration Register 1
// __CONFIG _CONFIG1, _CP_OFF & _CCP2_RC1 & _DEBUG_OFF & _VBOR_2_0 & BOREN_1 & _MCLR_OFF & _PWRTE_OFF & _WDT_OFF & _HS_OSC
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