📄 pic16f1526.h
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volatile unsigned char TRISD @ 0x08F;
// bit and bitfield definitions
volatile bit TRISD0 @ ((unsigned)&TRISD*8)+0;
volatile bit TRISD1 @ ((unsigned)&TRISD*8)+1;
volatile bit TRISD2 @ ((unsigned)&TRISD*8)+2;
volatile bit TRISD3 @ ((unsigned)&TRISD*8)+3;
volatile bit TRISD4 @ ((unsigned)&TRISD*8)+4;
volatile bit TRISD5 @ ((unsigned)&TRISD*8)+5;
volatile bit TRISD6 @ ((unsigned)&TRISD*8)+6;
volatile bit TRISD7 @ ((unsigned)&TRISD*8)+7;
#ifndef _LIB_BUILD
volatile union {
struct {
unsigned TRISD0 : 1;
unsigned TRISD1 : 1;
unsigned TRISD2 : 1;
unsigned TRISD3 : 1;
unsigned TRISD4 : 1;
unsigned TRISD5 : 1;
unsigned TRISD6 : 1;
unsigned TRISD7 : 1;
};
} TRISDbits @ 0x08F;
#endif
// Register: TRISE
// PORTE Data Direction Control Register
volatile unsigned char TRISE @ 0x090;
// bit and bitfield definitions
volatile bit TRISE0 @ ((unsigned)&TRISE*8)+0;
volatile bit TRISE1 @ ((unsigned)&TRISE*8)+1;
volatile bit TRISE2 @ ((unsigned)&TRISE*8)+2;
volatile bit TRISE3 @ ((unsigned)&TRISE*8)+3;
volatile bit TRISE4 @ ((unsigned)&TRISE*8)+4;
volatile bit TRISE5 @ ((unsigned)&TRISE*8)+5;
volatile bit TRISE6 @ ((unsigned)&TRISE*8)+6;
volatile bit TRISE7 @ ((unsigned)&TRISE*8)+7;
#ifndef _LIB_BUILD
volatile union {
struct {
unsigned TRISE0 : 1;
unsigned TRISE1 : 1;
unsigned TRISE2 : 1;
unsigned TRISE3 : 1;
unsigned TRISE4 : 1;
unsigned TRISE5 : 1;
unsigned TRISE6 : 1;
unsigned TRISE7 : 1;
};
} TRISEbits @ 0x090;
#endif
// Register: PIE1
// Peripheral Interrupt Enable Register 1
volatile unsigned char PIE1 @ 0x091;
// bit and bitfield definitions
// TMR1 Overflow Interrupt Enable bit
volatile bit TMR1IE @ ((unsigned)&PIE1*8)+0;
// TMR2 to PR2 Match Interrupt Enable bit
volatile bit TMR2IE @ ((unsigned)&PIE1*8)+1;
// CCP1 Interrupt Enable bit
volatile bit CCP1IE @ ((unsigned)&PIE1*8)+2;
// Master Synchronous Serial Port (MSSP) Interrupt Enable bit
volatile bit SSP1IE @ ((unsigned)&PIE1*8)+3;
// EUSART Transmit Interrupt Enable bit
volatile bit TX1IE @ ((unsigned)&PIE1*8)+4;
// EUSART Receive Interrupt Enable bit
volatile bit RC1IE @ ((unsigned)&PIE1*8)+5;
// A/D Converter Interrupt Enable bit
volatile bit ADIE @ ((unsigned)&PIE1*8)+6;
// Timer1 Gate Interrupt Enable bit
volatile bit TMR1GIE @ ((unsigned)&PIE1*8)+7;
volatile bit SSPIE @ ((unsigned)&PIE1*8)+3;
volatile bit TXIE @ ((unsigned)&PIE1*8)+4;
volatile bit RCIE @ ((unsigned)&PIE1*8)+5;
#ifndef _LIB_BUILD
volatile union {
struct {
unsigned TMR1IE : 1;
unsigned TMR2IE : 1;
unsigned CCP1IE : 1;
unsigned SSP1IE : 1;
unsigned TX1IE : 1;
unsigned RC1IE : 1;
unsigned ADIE : 1;
unsigned TMR1GIE : 1;
};
struct {
unsigned : 3;
unsigned SSPIE : 1;
unsigned TXIE : 1;
unsigned RCIE : 1;
};
} PIE1bits @ 0x091;
#endif
// Register: PIE2
// Peripheral Interrupt Enable Register 2
volatile unsigned char PIE2 @ 0x092;
// bit and bitfield definitions
// CCP2 Interrupt Enable bit
volatile bit CCP2IE @ ((unsigned)&PIE2*8)+0;
volatile bit TMR8IE @ ((unsigned)&PIE2*8)+1;
volatile bit TMR10IE @ ((unsigned)&PIE2*8)+2;
// MSSP Bus Collision Interrupt Interrupt Enable bit
volatile bit BCL1IE @ ((unsigned)&PIE2*8)+3;
volatile bit TMR3GIE @ ((unsigned)&PIE2*8)+5;
volatile bit TMR5GIE @ ((unsigned)&PIE2*8)+6;
// CCP2 Interrupt Enable bit
volatile bit OSFIE @ ((unsigned)&PIE2*8)+7;
volatile bit BCLIE @ ((unsigned)&PIE2*8)+3;
#ifndef _LIB_BUILD
volatile union {
struct {
unsigned CCP2IE : 1;
unsigned TMR8IE : 1;
unsigned TMR10IE : 1;
unsigned BCL1IE : 1;
unsigned : 1;
unsigned TMR3GIE : 1;
unsigned TMR5GIE : 1;
unsigned OSFIE : 1;
};
struct {
unsigned : 3;
unsigned BCLIE : 1;
};
} PIE2bits @ 0x092;
#endif
// Register: PIE3
// Peripheral Interrupt Enable Register 3
volatile unsigned char PIE3 @ 0x093;
// bit and bitfield definitions
volatile bit TMR3IE @ ((unsigned)&PIE3*8)+0;
volatile bit TMR4IE @ ((unsigned)&PIE3*8)+1;
volatile bit TMR5IE @ ((unsigned)&PIE3*8)+2;
volatile bit TMR6IE @ ((unsigned)&PIE3*8)+3;
volatile bit CCP3IE @ ((unsigned)&PIE3*8)+4;
volatile bit CCP4IE @ ((unsigned)&PIE3*8)+5;
volatile bit CCP5IE @ ((unsigned)&PIE3*8)+6;
volatile bit CCP6IE @ ((unsigned)&PIE3*8)+7;
#ifndef _LIB_BUILD
volatile union {
struct {
unsigned TMR3IE : 1;
unsigned TMR4IE : 1;
unsigned TMR5IE : 1;
unsigned TMR6IE : 1;
unsigned CCP3IE : 1;
unsigned CCP4IE : 1;
unsigned CCP5IE : 1;
unsigned CCP6IE : 1;
};
} PIE3bits @ 0x093;
#endif
// Register: PIE4
// Peripheral Interrupt Enable Register 4
volatile unsigned char PIE4 @ 0x094;
// bit and bitfield definitions
volatile bit SSP2IE @ ((unsigned)&PIE4*8)+0;
volatile bit BCL2IE @ ((unsigned)&PIE4*8)+1;
volatile bit CCP7IE @ ((unsigned)&PIE4*8)+2;
volatile bit CCP8IE @ ((unsigned)&PIE4*8)+3;
volatile bit TX2IE @ ((unsigned)&PIE4*8)+4;
volatile bit RC2IE @ ((unsigned)&PIE4*8)+5;
volatile bit CCP9IE @ ((unsigned)&PIE4*8)+6;
volatile bit CCP10IE @ ((unsigned)&PIE4*8)+7;
#ifndef _LIB_BUILD
volatile union {
struct {
unsigned SSP2IE : 1;
unsigned BCL2IE : 1;
unsigned CCP7IE : 1;
unsigned CCP8IE : 1;
unsigned TX2IE : 1;
unsigned RC2IE : 1;
unsigned CCP9IE : 1;
unsigned CCP10IE : 1;
};
} PIE4bits @ 0x094;
#endif
// Register: OPTION_REG
// Option Register
volatile unsigned char OPTION_REG @ 0x095;
// bit and bitfield definitions
// Prescaler Active bit
volatile bit PSA @ ((unsigned)&OPTION_REG*8)+3;
// TMR0 Source Edge Select bit
volatile bit TMR0SE @ ((unsigned)&OPTION_REG*8)+4;
// TMR0 Clock Source Select bit
volatile bit TMR0CS @ ((unsigned)&OPTION_REG*8)+5;
// Interrupt Edge Select bit
volatile bit INTEDG @ ((unsigned)&OPTION_REG*8)+6;
// Weak Pull-up Enable bit
volatile bit nWPUEN @ ((unsigned)&OPTION_REG*8)+7;
volatile bit PS0 @ ((unsigned)&OPTION_REG*8)+0;
volatile bit PS1 @ ((unsigned)&OPTION_REG*8)+1;
volatile bit PS2 @ ((unsigned)&OPTION_REG*8)+2;
volatile bit T0SE @ ((unsigned)&OPTION_REG*8)+4;
volatile bit T0CS @ ((unsigned)&OPTION_REG*8)+5;
#ifndef _LIB_BUILD
volatile union {
struct {
unsigned PS : 3;
unsigned PSA : 1;
unsigned TMR0SE : 1;
unsigned TMR0CS : 1;
unsigned INTEDG : 1;
unsigned nWPUEN : 1;
};
struct {
unsigned PS0 : 1;
unsigned PS1 : 1;
unsigned PS2 : 1;
unsigned : 1;
unsigned T0SE : 1;
unsigned T0CS : 1;
};
} OPTION_REGbits @ 0x095;
#endif
// Register: PCON
// Power Control Register
volatile unsigned char PCON @ 0x096;
// bit and bitfield definitions
// Brown-out Reset Status bit
volatile bit nBOR @ ((unsigned)&PCON*8)+0;
// Power-on Reset Status bit
volatile bit nPOR @ ((unsigned)&PCON*8)+1;
// RESET Instruction Flag bit
volatile bit nRI @ ((unsigned)&PCON*8)+2;
// MCLR Reset Flag bit
volatile bit nRMCLR @ ((unsigned)&PCON*8)+3;
volatile bit nRWDT @ ((unsigned)&PCON*8)+4;
// Stack Underflow Flag bit
volatile bit STKUNF @ ((unsigned)&PCON*8)+6;
// Stack Overflow Flag bit
volatile bit STKOVF @ ((unsigned)&PCON*8)+7;
#ifndef _LIB_BUILD
volatile union {
struct {
unsigned nBOR : 1;
unsigned nPOR : 1;
unsigned nRI : 1;
unsigned nRMCLR : 1;
unsigned nRWDT : 1;
unsigned : 1;
unsigned STKUNF : 1;
unsigned STKOVF : 1;
};
} PCONbits @ 0x096;
#endif
// Register: WDTCON
// Watchdog Timer Control Register
volatile unsigned char WDTCON @ 0x097;
// bit and bitfield definitions
// Software Enable/Disable for Watch Dog Timer bit
volatile bit SWDTEN @ ((unsigned)&WDTCON*8)+0;
// Watchdog Timer Period Select bits
volatile bit WDTPS0 @ ((unsigned)&WDTCON*8)+1;
// Watchdog Timer Period Select bits
volatile bit WDTPS1 @ ((unsigned)&WDTCON*8)+2;
// Watchdog Timer Period Select bits
volatile bit WDTPS2 @ ((unsigned)&WDTCON*8)+3;
// Watchdog Timer Period Select bits
volatile bit WDTPS3 @ ((unsigned)&WDTCON*8)+4;
// Watchdog Timer Period Select bits
volatile bit WDTPS4 @ ((unsigned)&WDTCON*8)+5;
#ifndef _LIB_BUILD
volatile union {
struct {
unsigned SWDTEN : 1;
unsigned WDTPS0 : 1;
unsigned WDTPS1 : 1;
unsigned WDTPS2 : 1;
unsigned WDTPS3 : 1;
unsigned WDTPS4 : 1;
};
struct {
unsigned : 1;
unsigned WDTPS : 5;
};
} WDTCONbits @ 0x097;
#endif
// Register: OSCCON
// Oscillator Control Register
volatile unsigned char OSCCON @ 0x099;
// bit and bitfield definitions
// System clock select bit
volatile bit SCS0 @ ((unsigned)&OSCCON*8)+0;
// System clock select bit
volatile bit SCS1 @ ((unsigned)&OSCCON*8)+1;
// Internal Oscillator Frequency Select bits
volatile bit IRCF0 @ ((unsigned)&OSCCON*8)+3;
// Internal Oscillator Frequency Select bits
volatile bit IRCF1 @ ((unsigned)&OSCCON*8)+4;
// Internal Oscillator Frequency Select bits
volatile bit IRCF2 @ ((unsigned)&OSCCON*8)+5;
// Internal Oscillator Frequency Select bits
volatile bit IRCF3 @ ((unsigned)&OSCCON*8)+6;
#ifndef _LIB_BUILD
volatile union {
struct {
unsigned SCS0 : 1;
unsigned SCS1 : 1;
unsigned : 1;
unsigned IRCF0 : 1;
unsigned IRCF1 : 1;
unsigned IRCF2 : 1;
unsigned IRCF3 : 1;
unsigned : 1;
};
struct {
unsigned SCS : 2;
unsigned : 1;
unsigned IRCF : 4;
};
} OSCCONbits @ 0x099;
#endif
// Register: OSCSTAT
// Oscillator Status Register
volatile unsigned char OSCSTAT @ 0x09A;
// bit and bitfield definitions
// Low Freqency Internal Oscillator Ready bit
volatile bit HFIOFS @ ((unsigned)&OSCSTAT*8)+0;
// Low Freqency Internal Oscillator Ready bit
volatile bit LFIOFR @ ((unsigned)&OSCSTAT*8)+1;
volatile bit HFIOFR @ ((unsigned)&OSCSTAT*8)+4;
// Oscillator Start-up Time-out Status bit
volatile bit OSTS @ ((unsigned)&OSCSTAT*8)+5;
// Timer1 Oscillator Ready bit
volatile bit T1OSCR @ ((unsigned)&OSCSTAT*8)+7;
#ifndef _LIB_BUILD
volatile union {
struct {
unsigned HFIOFS : 1;
unsigned LFIOFR : 1;
unsigned : 1;
unsigned : 1;
unsigned HFIOFR : 1;
unsigned OSTS : 1;
unsigned : 1;
unsigned T1OSCR : 1;
};
} OSCSTATbits @ 0x09A;
#endif
// bit and bitfield definitions
// Register: ADRESL
// A/D Result Register LSB
volatile unsigned char ADRESL @ 0x09B;
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