📄 pic12f1840.h
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// bit and bitfield definitions
// DAC1 Voltage Output Select bits
volatile bit DACR0 @ ((unsigned)&DACCON1*8)+0;
// DAC1 Voltage Output Select bits
volatile bit DACR1 @ ((unsigned)&DACCON1*8)+1;
// DAC1 Voltage Output Select bits
volatile bit DACR2 @ ((unsigned)&DACCON1*8)+2;
// DAC1 Voltage Output Select bits
volatile bit DACR3 @ ((unsigned)&DACCON1*8)+3;
// DAC1 Voltage Output Select bits
volatile bit DACR4 @ ((unsigned)&DACCON1*8)+4;
#ifndef _LIB_BUILD
volatile union {
struct {
unsigned DACR0 : 1;
unsigned DACR1 : 1;
unsigned DACR2 : 1;
unsigned DACR3 : 1;
unsigned DACR4 : 1;
unsigned : 1;
};
struct {
unsigned DACR : 5;
};
} DACCON1bits @ 0x119;
#endif
// Register: SRCON0
// SR Latch Control Register 0
volatile unsigned char SRCON0 @ 0x11A;
// bit and bitfield definitions
// Pulse Reset Input of the SR Latch
volatile bit SRPR @ ((unsigned)&SRCON0*8)+0;
// Pulse Set Input of the SR Latch
volatile bit SRPS @ ((unsigned)&SRCON0*8)+1;
// SR Latch Q Output Enable bit
volatile bit SRNQEN @ ((unsigned)&SRCON0*8)+2;
// SR Latch Q Output Enable bit
volatile bit SRQEN @ ((unsigned)&SRCON0*8)+3;
// SR Latch Clock divider bits
volatile bit SRCLK0 @ ((unsigned)&SRCON0*8)+4;
// SR Latch Clock divider bits
volatile bit SRCLK1 @ ((unsigned)&SRCON0*8)+5;
// SR Latch Clock divider bits
volatile bit SRCLK2 @ ((unsigned)&SRCON0*8)+6;
// SR Latch Enable bit
volatile bit SRLEN @ ((unsigned)&SRCON0*8)+7;
#ifndef _LIB_BUILD
volatile union {
struct {
unsigned SRPR : 1;
unsigned SRPS : 1;
unsigned SRNQEN : 1;
unsigned SRQEN : 1;
unsigned SRCLK0 : 1;
unsigned SRCLK1 : 1;
unsigned SRCLK2 : 1;
unsigned SRLEN : 1;
};
struct {
unsigned : 4;
unsigned SRCLK : 3;
};
} SRCON0bits @ 0x11A;
#endif
// Register: SRCON1
// SR Latch Control Register 1
volatile unsigned char SRCON1 @ 0x11B;
// bit and bitfield definitions
// SR Latch C1 Reset Enable bit
volatile bit SRRC1E @ ((unsigned)&SRCON1*8)+0;
// SR Latch Reset Clock Enable bit
volatile bit SRRCKE @ ((unsigned)&SRCON1*8)+2;
// SR Latch Peripheral Reset Enable bit
volatile bit SRRPE @ ((unsigned)&SRCON1*8)+3;
// SR Latch C1 Set Enable bit
volatile bit SRSC1E @ ((unsigned)&SRCON1*8)+4;
// SR Latch Set Clock Enable bit
volatile bit SRSCKE @ ((unsigned)&SRCON1*8)+6;
// SR Latch Peripheral Set Enable bit
volatile bit SRSPE @ ((unsigned)&SRCON1*8)+7;
#ifndef _LIB_BUILD
volatile union {
struct {
unsigned SRRC1E : 1;
unsigned : 1;
unsigned SRRCKE : 1;
unsigned SRRPE : 1;
unsigned SRSC1E : 1;
unsigned : 1;
unsigned SRSCKE : 1;
unsigned SRSPE : 1;
};
} SRCON1bits @ 0x11B;
#endif
// Register: APFCON
// Alternate Pin Function Control Register
volatile unsigned char APFCON @ 0x11D;
volatile unsigned char APFCON0 @ 0x11D;
// bit and bitfield definitions
// CCP1 Pin Selection
volatile bit CCP1SEL @ ((unsigned)&APFCON*8)+0;
// P1B Pin Selection
volatile bit P1BSEL @ ((unsigned)&APFCON*8)+1;
// TX/CK Pin Selection
volatile bit TXCKSEL @ ((unsigned)&APFCON*8)+2;
// Timer 1 Gate Pin Selection
volatile bit T1GSEL @ ((unsigned)&APFCON*8)+3;
// SS Pin Selection
volatile bit SSSEL @ ((unsigned)&APFCON*8)+5;
// SDO Pin Selection
volatile bit SDOSEL @ ((unsigned)&APFCON*8)+6;
// RX/DT Pin Selection
volatile bit RXDTSEL @ ((unsigned)&APFCON*8)+7;
volatile bit SS1SEL @ ((unsigned)&APFCON*8)+5;
volatile bit SDO1SEL @ ((unsigned)&APFCON*8)+6;
#ifndef _LIB_BUILD
volatile union {
struct {
unsigned CCP1SEL : 1;
unsigned P1BSEL : 1;
unsigned TXCKSEL : 1;
unsigned T1GSEL : 1;
unsigned : 1;
unsigned SSSEL : 1;
unsigned SDOSEL : 1;
unsigned RXDTSEL : 1;
};
struct {
unsigned : 5;
unsigned SS1SEL : 1;
unsigned SDO1SEL : 1;
};
} APFCONbits @ 0x11D;
#endif
//
// Special function register definitions: Bank 3
//
// Register: ANSELA
volatile unsigned char ANSELA @ 0x18C;
// bit and bitfield definitions
volatile bit ANSA0 @ ((unsigned)&ANSELA*8)+0;
volatile bit ANSA1 @ ((unsigned)&ANSELA*8)+1;
volatile bit ANSA2 @ ((unsigned)&ANSELA*8)+2;
volatile bit ANSA4 @ ((unsigned)&ANSELA*8)+4;
#ifndef _LIB_BUILD
volatile union {
struct {
unsigned ANSA0 : 1;
unsigned ANSA1 : 1;
unsigned ANSA2 : 1;
unsigned : 1;
unsigned ANSA4 : 1;
unsigned : 1;
unsigned : 1;
unsigned : 1;
};
struct {
unsigned ANSELA : 5;
unsigned : 1;
};
} ANSELAbits @ 0x18C;
#endif
// bit and bitfield definitions
// Register: EEADRL
volatile unsigned char EEADRL @ 0x191;
// bit and bitfield definitions
// Register: EEADRH
volatile unsigned char EEADRH @ 0x192;
// bit and bitfield definitions
#ifndef _LIB_BUILD
volatile union {
struct {
unsigned EEADRH : 7;
};
} EEADRHbits @ 0x192;
#endif
// Register: EEADR
volatile unsigned int EEADR @ 0x191;
// bit and bitfield definitions
// Register: EEDATL
volatile unsigned char EEDATL @ 0x193;
volatile unsigned char EEDATA @ 0x193;
// bit and bitfield definitions
// Register: EEDATH
volatile unsigned char EEDATH @ 0x194;
// bit and bitfield definitions
#ifndef _LIB_BUILD
volatile union {
struct {
unsigned EEDATH : 6;
};
} EEDATHbits @ 0x194;
#endif
// Register: EEDAT
volatile unsigned int EEDAT @ 0x193;
// Register: EECON1
volatile unsigned char EECON1 @ 0x195;
// bit and bitfield definitions
// Read Control bit
volatile bit RD @ ((unsigned)&EECON1*8)+0;
// Write Control bit
volatile bit WR @ ((unsigned)&EECON1*8)+1;
// Program/Erase Enable bit
volatile bit WREN @ ((unsigned)&EECON1*8)+2;
// Sequence Error Flag bit
volatile bit WRERR @ ((unsigned)&EECON1*8)+3;
// Program FLASH Erase Enable bit
volatile bit FREE @ ((unsigned)&EECON1*8)+4;
// Load Write Latches Only bit
volatile bit LWLO @ ((unsigned)&EECON1*8)+5;
// FLASH Program / Data EEPROM or Configuration Select bit
volatile bit CFGS @ ((unsigned)&EECON1*8)+6;
// FLASH Program / Data EEPROM Memory Select bit
volatile bit EEPGD @ ((unsigned)&EECON1*8)+7;
#ifndef _LIB_BUILD
volatile union {
struct {
unsigned RD : 1;
unsigned WR : 1;
unsigned WREN : 1;
unsigned WRERR : 1;
unsigned FREE : 1;
unsigned LWLO : 1;
unsigned CFGS : 1;
unsigned EEPGD : 1;
};
} EECON1bits @ 0x195;
#endif
// Register: EECON2
volatile unsigned char EECON2 @ 0x196;
// bit and bitfield definitions
// Register: VREGCON
volatile unsigned char VREGCON @ 0x197;
// bit and bitfield definitions
volatile bit VREGPM0 @ ((unsigned)&VREGCON*8)+0;
volatile bit VREGPM1 @ ((unsigned)&VREGCON*8)+1;
#ifndef _LIB_BUILD
volatile union {
struct {
unsigned VREGPM0 : 1;
unsigned VREGPM1 : 1;
};
struct {
unsigned VREGPM : 2;
};
} VREGCONbits @ 0x197;
#endif
// Register: RCREG
volatile unsigned char RCREG @ 0x199;
// bit and bitfield definitions
// Register: TXREG
volatile unsigned char TXREG @ 0x19A;
// bit and bitfield definitions
// Register: SPBRGL
volatile unsigned char SPBRGL @ 0x19B;
volatile unsigned char SPBRG @ 0x19B;
// bit and bitfield definitions
// Register: SPBRGH
volatile unsigned char SPBRGH @ 0x19C;
// bit and bitfield definitions
// Register: RCSTA
// Receive Status and Control Register
volatile unsigned char RCSTA @ 0x19D;
// bit and bitfield definitions
// 9th bit of received data (can be parity bit)
volatile bit RX9D @ ((unsigned)&RCSTA*8)+0;
// Overrun Error bit
volatile bit OERR @ ((unsigned)&RCSTA*8)+1;
// Framing Error bit
volatile bit FERR @ ((unsigned)&RCSTA*8)+2;
// Address Detect Enable bit
volatile bit ADDEN @ ((unsigned)&RCSTA*8)+3;
// Continuous Receive Enable bit
volatile bit CREN @ ((unsigned)&RCSTA*8)+4;
// Single Receive Enable bit
volatile bit SREN @ ((unsigned)&RCSTA*8)+5;
// 9-bit Receive Enable bit
volatile bit RX9 @ ((unsigned)&RCSTA*8)+6;
// Serial Port Enable bit
volatile bit SPEN @ ((unsigned)&RCSTA*8)+7;
#ifndef _LIB_BUILD
volatile union {
struct {
unsigned RX9D : 1;
unsigned OERR : 1;
unsigned FERR : 1;
unsigned ADDEN : 1;
unsigned CREN : 1;
unsigned SREN : 1;
unsigned RX9 : 1;
unsigned SPEN : 1;
};
} RCSTAbits @ 0x19D;
#endif
// Register: TXSTA
// Transmit Status and Control Register
volatile unsigned char TXSTA @ 0x19E;
// bit and bitfield definitions
// 9th bit of transmit data; can be used as parity bit
volatile bit TX9D @ ((unsigned)&TXSTA*8)+0;
// Transmit Operation Idle Status bit
volatile bit TRMT @ ((unsigned)&TXSTA*8)+1;
// High Baud Rate Select bit
volatile bit BRGH @ ((unsigned)&TXSTA*8)+2;
// Send BREAK character bit
volatile bit SENDB @ ((unsigned)&TXSTA*8)+3;
// USART Mode Select bit
volatile bit SYNC @ ((unsigned)&TXSTA*8)+4;
// Transmit Enable bit
volatile bit TXEN @ ((unsigned)&TXSTA*8)+5;
// 9-bit Transmit Enable bit
volatile bit TX9 @ ((unsigned)&TXSTA*8)+6;
// Clock Source Select bit
volatile bit CSRC @ ((unsigned)&TXSTA*8)+7;
#ifndef _LIB_BUILD
volatile union {
struct {
unsigned TX9D : 1;
unsigned TRMT : 1;
unsigned BRGH : 1;
unsigned SENDB : 1;
unsigned SYNC : 1;
unsigned TXEN : 1;
unsigned TX9 : 1;
unsigned CSRC : 1;
};
} TXSTAbits @ 0x19E;
#endif
// Register: BAUDCON
// Baud Rate Control Register
volatile unsigned char BAUDCON @ 0x19F;
// bit and bitfield definitions
// Auto-Baud Detect Enable bit
volatile bit ABDEN @ ((unsigned)&BAUDCON*8)+0;
// Wake-Up Enable bit
volatile bit WUE @ ((unsigned)&BAUDCON*8)+1;
// 16-bit Baud Rate Register enable bit
volatile bit BRG16 @ ((unsigned)&BAUDCON*8)+3;
// Clock/Transmit Polarity Select bit
volatile bit SCKP @ ((unsigned)&BAUDCON*8)+4;
// Receive Operation Idle Status bit
volatile bit RCIDL @ ((unsigned)&BAUDCON*8)+6;
// BRG Rollover Status bit
volatile bit ABDOVF @ ((unsigned)&BAUDCON*8)+7;
#ifndef _LIB_BUILD
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