📄 pic177xx.h
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static bit DC0PW2 @ (unsigned)&PW2DCL*8+6;
static bit TM2PW2 @ (unsigned)&PW2DCL*8+5;
/* PW1DCH bits */
static bit DC9PW1 @ (unsigned)&PW1DCH*8+7;
static bit DC8PW1 @ (unsigned)&PW1DCH*8+6;
static bit DC7PW1 @ (unsigned)&PW1DCH*8+5;
static bit DC6PW1 @ (unsigned)&PW1DCH*8+4;
static bit DC5PW1 @ (unsigned)&PW1DCH*8+3;
static bit DC4PW1 @ (unsigned)&PW1DCH*8+2;
static bit DC3PW1 @ (unsigned)&PW1DCH*8+1;
static bit DC2PW1 @ (unsigned)&PW1DCH*8+0;
/* PW2DCH bits */
static bit DC9PW2 @ (unsigned)&PW2DCH*8+7;
static bit DC8PW2 @ (unsigned)&PW2DCH*8+6;
static bit DC7PW2 @ (unsigned)&PW2DCH*8+5;
static bit DC6PW2 @ (unsigned)&PW2DCH*8+4;
static bit DC5PW2 @ (unsigned)&PW2DCH*8+3;
static bit DC4PW2 @ (unsigned)&PW2DCH*8+2;
static bit DC3PW2 @ (unsigned)&PW2DCH*8+1;
static bit DC2PW2 @ (unsigned)&PW2DCH*8+0;
/* TCON1 bits */
static bit CA2ED1 @ (unsigned)&TCON1*8+7;
static bit CA2ED0 @ (unsigned)&TCON1*8+6;
static bit CA1ED1 @ (unsigned)&TCON1*8+5;
static bit CA1ED0 @ (unsigned)&TCON1*8+4;
static bit T16 @ (unsigned)&TCON1*8+3;
static bit TMR3CS @ (unsigned)&TCON1*8+2;
static bit TMR2CS @ (unsigned)&TCON1*8+1;
static bit TMR1CS @ (unsigned)&TCON1*8+0;
/* TCON2 bits */
static volatile bit CA2OVF @ (unsigned)&TCON2*8+7;
static volatile bit CA1OVF @ (unsigned)&TCON2*8+6;
static volatile bit PWM2ON @ (unsigned)&TCON2*8+5;
static volatile bit PWM1ON @ (unsigned)&TCON2*8+4;
static bit CA1 @ (unsigned)&TCON2*8+3;
static bit TMR3ON @ (unsigned)&TCON2*8+2;
static bit TMR2ON @ (unsigned)&TCON2*8+1;
static bit TMR1ON @ (unsigned)&TCON2*8+0;
/* PIR2 bits */
static volatile bit SSPIF @ (unsigned)&PIR2*8+7;
static volatile bit BCLIF @ (unsigned)&PIR2*8+6;
static volatile bit ADIF @ (unsigned)&PIR2*8+5;
static volatile bit CA4IF @ (unsigned)&PIR2*8+3;
static volatile bit CA3IF @ (unsigned)&PIR2*8+2;
static volatile bit TX2IF @ (unsigned)&PIR2*8+1;
static volatile bit RC2IF @ (unsigned)&PIR2*8+0;
/* PIE2 bits */
static bit SSPIE @ (unsigned)&PIE2*8+7;
static bit BCLIE @ (unsigned)&PIE2*8+6;
static bit ADIE @ (unsigned)&PIE2*8+5;
static bit CA4IE @ (unsigned)&PIE2*8+3;
static bit CA3IE @ (unsigned)&PIE2*8+2;
static bit TX2IE @ (unsigned)&PIE2*8+1;
static bit RC2IE @ (unsigned)&PIE2*8+0;
/* RCSTA2 bits */
static bit SPEN2 @ (unsigned)&RCSTA2*8+7;
static bit RX92 @ (unsigned)&RCSTA2*8+6;
static bit SREN2 @ (unsigned)&RCSTA2*8+5;
static bit CREN2 @ (unsigned)&RCSTA2*8+4;
static volatile bit FERR2 @ (unsigned)&RCSTA2*8+2;
static volatile bit OERR2 @ (unsigned)&RCSTA2*8+1;
static volatile bit RX9D2 @ (unsigned)&RCSTA2*8+0;
/* TXSTA2 bits */
static bit CSRC2 @ (unsigned)&TXSTA2*8+7;
static bit TX92 @ (unsigned)&TXSTA2*8+6;
static bit TXEN2 @ (unsigned)&TXSTA2*8+5;
static bit SYNC2 @ (unsigned)&TXSTA2*8+4;
static volatile bit TRMT2 @ (unsigned)&TXSTA2*8+1;
static bit TX9D2 @ (unsigned)&TXSTA2*8+0;
/* PORTF bits */
static volatile bit RF7 @ (unsigned)&PORTF*8+7;
static volatile bit RF6 @ (unsigned)&PORTF*8+6;
static volatile bit RF5 @ (unsigned)&PORTF*8+5;
static volatile bit RF4 @ (unsigned)&PORTF*8+4;
static volatile bit RF3 @ (unsigned)&PORTF*8+3;
static volatile bit RF2 @ (unsigned)&PORTF*8+2;
static volatile bit RF1 @ (unsigned)&PORTF*8+1;
static volatile bit RF0 @ (unsigned)&PORTF*8+0;
/* DDRF bits */
static bit DDRF7 @ (unsigned)&DDRF*8+7;
static bit DDRF6 @ (unsigned)&DDRF*8+6;
static bit DDRF5 @ (unsigned)&DDRF*8+5;
static bit DDRF4 @ (unsigned)&DDRF*8+4;
static bit DDRF3 @ (unsigned)&DDRF*8+3;
static bit DDRF2 @ (unsigned)&DDRF*8+2;
static bit DDRF1 @ (unsigned)&DDRF*8+1;
static bit DDRF0 @ (unsigned)&DDRF*8+0;
/* PORTG bits */
static volatile bit RG7 @ (unsigned)&PORTG*8+7;
static volatile bit RG6 @ (unsigned)&PORTG*8+6;
static volatile bit RG5 @ (unsigned)&PORTG*8+5;
static volatile bit RG4 @ (unsigned)&PORTG*8+4;
static volatile bit RG3 @ (unsigned)&PORTG*8+3;
static volatile bit RG2 @ (unsigned)&PORTG*8+2;
static volatile bit RG1 @ (unsigned)&PORTG*8+1;
static volatile bit RG0 @ (unsigned)&PORTG*8+0;
/* DDRG bits */
static bit DDRG7 @ (unsigned)&DDRG*8+7;
static bit DDRG6 @ (unsigned)&DDRG*8+6;
static bit DDRG5 @ (unsigned)&DDRG*8+5;
static bit DDRG4 @ (unsigned)&DDRG*8+4;
static bit DDRG3 @ (unsigned)&DDRG*8+3;
static bit DDRG2 @ (unsigned)&DDRG*8+2;
static bit DDRG1 @ (unsigned)&DDRG*8+1;
static bit DDRG0 @ (unsigned)&DDRG*8+0;
/* ADCON0 bits */
static bit CHS3 @ (unsigned)&ADCON0*8+7;
static bit CHS2 @ (unsigned)&ADCON0*8+6;
static bit CHS1 @ (unsigned)&ADCON0*8+5;
static bit CHS0 @ (unsigned)&ADCON0*8+4;
static volatile bit GO @ (unsigned)&ADCON0*8+2;
static bit ADON @ (unsigned)&ADCON0*8+0;
/* ADCON1 bits */
static bit ADCS1 @ (unsigned)&ADCON1*8+7;
static bit ADCS0 @ (unsigned)&ADCON1*8+6;
static bit ADFM @ (unsigned)&ADCON1*8+5;
static bit PCFG3 @ (unsigned)&ADCON1*8+3;
static bit PCFG2 @ (unsigned)&ADCON1*8+2;
static bit PCFG1 @ (unsigned)&ADCON1*8+1;
static bit PCFG0 @ (unsigned)&ADCON1*8+0;
/* SSPCON1 bits */
static volatile bit WCOL @ (unsigned)&SSPCON1*8+7;
static volatile bit SSPOV @ (unsigned)&SSPCON1*8+6;
static bit SSPEN @ (unsigned)&SSPCON1*8+5;
static bit CKP @ (unsigned)&SSPCON1*8+4;
static bit SSPM3 @ (unsigned)&SSPCON1*8+3;
static bit SSPM2 @ (unsigned)&SSPCON1*8+2;
static bit SSPM1 @ (unsigned)&SSPCON1*8+1;
static bit SSPM0 @ (unsigned)&SSPCON1*8+0;
/* SSPCON2 bits */
static bit GCEN @ (unsigned)&SSPCON2*8+7;
static volatile bit ACKSTAT @ (unsigned)&SSPCON2*8+6;
static bit ACKDT @ (unsigned)&SSPCON2*8+5;
static bit ACKEN @ (unsigned)&SSPCON2*8+4;
static bit RCEN @ (unsigned)&SSPCON2*8+3;
static volatile bit PEN @ (unsigned)&SSPCON2*8+2;
static volatile bit RSEN @ (unsigned)&SSPCON2*8+1;
static volatile bit SEN @ (unsigned)&SSPCON2*8+0;
/* SSPSTAT bits */
static bit SMP @ (unsigned)&SSPSTAT*8+7;
static bit CKE @ (unsigned)&SSPSTAT*8+6;
static bit DA @ (unsigned)&SSPSTAT*8+5;
static bit STOP @ (unsigned)&SSPSTAT*8+4;
static bit START @ (unsigned)&SSPSTAT*8+3;
static bit RW @ (unsigned)&SSPSTAT*8+2;
static bit UA @ (unsigned)&SSPSTAT*8+1;
static bit BF @ (unsigned)&SSPSTAT*8+0;
#ifdef __STAT_BACKWARD_COMPATIBILITY
#define STAT_SMP SMP
#define STAT_CKE CKE
#define STAT_DA DA
#define STAT_P STOP
#define STAT_S START
#define STAT_RW RW
#define STAT_UA UA
#define STAT_BF BF
#endif
/* PW3DCL bits */
static bit DC1PW3 @ (unsigned)&PW3DCL*8+7;
static bit DC0PW3 @ (unsigned)&PW3DCL*8+6;
static bit TM2PW3 @ (unsigned)&PW3DCL*8+5;
/* PW3DCH bits */
static bit DC9PW3 @ (unsigned)&PW3DCH*8+7;
static bit DC8PW3 @ (unsigned)&PW3DCH*8+6;
static bit DC7PW3 @ (unsigned)&PW3DCH*8+5;
static bit DC6PW3 @ (unsigned)&PW3DCH*8+4;
static bit DC5PW3 @ (unsigned)&PW3DCH*8+3;
static bit DC4PW3 @ (unsigned)&PW3DCH*8+2;
static bit DC3PW3 @ (unsigned)&PW3DCH*8+1;
static bit DC2PW3 @ (unsigned)&PW3DCH*8+0;
/* TCON3 bits */
static volatile bit CA4OVF @ (unsigned)&TCON3*8+6;
static volatile bit CA3OVF @ (unsigned)&TCON3*8+5;
static bit CA4ED1 @ (unsigned)&TCON3*8+4;
static bit CA4ED0 @ (unsigned)&TCON3*8+3;
static bit CA3ED1 @ (unsigned)&TCON3*8+2;
static bit CA3ED0 @ (unsigned)&TCON3*8+1;
static bit PWM3ON @ (unsigned)&TCON3*8+0;
#if defined(_17C762) || defined(_17C766)
/* PORTH bits */
static volatile bit RH7 @ (unsigned)&PORTH*8+7;
static volatile bit RH6 @ (unsigned)&PORTH*8+6;
static volatile bit RH5 @ (unsigned)&PORTH*8+5;
static volatile bit RH4 @ (unsigned)&PORTH*8+4;
static volatile bit RH3 @ (unsigned)&PORTH*8+3;
static volatile bit RH2 @ (unsigned)&PORTH*8+2;
static volatile bit RH1 @ (unsigned)&PORTH*8+1;
static volatile bit RH0 @ (unsigned)&PORTH*8+0;
/* PORTJ bits */
static volatile bit RJ7 @ (unsigned)&PORTJ*8+7;
static volatile bit RJ6 @ (unsigned)&PORTJ*8+6;
static volatile bit RJ5 @ (unsigned)&PORTJ*8+5;
static volatile bit RJ4 @ (unsigned)&PORTJ*8+4;
static volatile bit RJ3 @ (unsigned)&PORTJ*8+3;
static volatile bit RJ2 @ (unsigned)&PORTJ*8+2;
static volatile bit RJ1 @ (unsigned)&PORTJ*8+1;
static volatile bit RJ0 @ (unsigned)&PORTJ*8+0;
/* DDRH bits */
static bit DDRH7 @ (unsigned)&DDRH*8+7;
static bit DDRH6 @ (unsigned)&DDRH*8+6;
static bit DDRH5 @ (unsigned)&DDRH*8+5;
static bit DDRH4 @ (unsigned)&DDRH*8+4;
static bit DDRH3 @ (unsigned)&DDRH*8+3;
static bit DDRH2 @ (unsigned)&DDRH*8+2;
static bit DDRH1 @ (unsigned)&DDRH*8+1;
static bit DDRH0 @ (unsigned)&DDRH*8+0;
/* DDRJ bits */
static bit DDRJ7 @ (unsigned)&DDRJ*8+7;
static bit DDRJ6 @ (unsigned)&DDRJ*8+6;
static bit DDRJ5 @ (unsigned)&DDRJ*8+5;
static bit DDRJ4 @ (unsigned)&DDRJ*8+4;
static bit DDRJ3 @ (unsigned)&DDRJ*8+3;
static bit DDRJ2 @ (unsigned)&DDRJ*8+2;
static bit DDRJ1 @ (unsigned)&DDRJ*8+1;
static bit DDRJ0 @ (unsigned)&DDRJ*8+0;
#endif
#if 0
/* TSTMD1 bits */
static bit FPMM2 @ (unsigned)&TSTMD1*8+7;
static bit BODEN1 @ (unsigned)&TSTMD1*8+6;
static bit ADTST @ (unsigned)&TSTMD1*8+0;
/* TSTMD2 bits */
static bit TSTMUX @ (unsigned)&TSTMD2*8+7;
static bit FPMM1 @ (unsigned)&TSTMD2*8+6;
static bit GLWP @ (unsigned)&TSTMD2*8+5;
static bit FPMM0 @ (unsigned)&TSTMD2*8+4;
static bit NWDT1 @ (unsigned)&TSTMD2*8+3;
static bit NWDT0 @ (unsigned)&TSTMD2*8+2;
static bit SOSC1 @ (unsigned)&TSTMD2*8+1;
static bit SOSC0 @ (unsigned)&TSTMD2*8+0;
#endif
#define CONFIG_ADDR 0xFE00
/*osc configurations*/
#define EC 0xFFFF // external clock
#define XT 0xFFFE // crystal/resonator
#define RC 0xFFFD // external resistor/capacitor
#define LF 0xFFFC // low frequency
/*watchdog timer postscaler*/
#define WDTPS1 0xFFFF // postscaler = 1
#define WDTPS256 0xFFFB // postscaler = 256
#define WDTPS64 0xFFF7 // postscaler = 64
#define WDTDIS 0xFFF3 // watchdog timer is disabled
/*brown out reset*/
#define BOREN 0xFFFF // enable brown out reset
#define BORDIS 0xBFFF // disable brown out reset
/* PM2, PM1, PM0 Processor mode select */
#define PROTECT 0xBFAF /* code protected microcontroller mode */
#define MICROPROCESSOR 0xFFFF /* microprocessor mode */
#define MICROCONTROLLER 0xFFEF /* microcontroller mode */
#define EXT_MICROCTRL 0xFFBF /* extended microcontroller mode */
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