📄 pic177xx.h
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#ifndef _HTC_H_
#warning Header file pic177xx.h included directly. Use #include <htc.h> instead.
#endif
/*
* Header file for the Microchip :
* PIC 17c752 chip
* PIC 17c756 chip
* PIC 17C756A chip
* PIC 17C762 chip
* PIC 17C766 chip
* High-end Microcontroller
*/
static unsigned char FSR0 @ 0x01;
static volatile unsigned char PCL @ 0x02;
static volatile unsigned char PCLATH @ 0x03;
static volatile unsigned char ALUSTA @ 0x04;
static unsigned char T0STA @ 0x05;
static volatile unsigned char CPUSTA @ 0x06;
static volatile unsigned char INTSTA @ 0x07;
static volatile unsigned char INDF1 @ 0x08;
static unsigned char FSR1 @ 0x09;
static volatile unsigned char WREG @ 0x0A;
static volatile unsigned char TMR0L @ 0x0B;
static volatile unsigned char TMR0H @ 0x0C;
static volatile unsigned int TMR0 @ 0x0B;
static volatile unsigned char TBLPTRL @ 0x0D;
static volatile unsigned char TBLPTRH @ 0x0E;
static unsigned char BSR @ 0x0F;
static volatile unsigned char PRODL @ 0x18;
static volatile unsigned char PRODH @ 0x19;
/* Bank 0 */
static volatile unsigned char PORTA @ 0x10;
static unsigned char DDRB @ 0x11;
static volatile unsigned char PORTB @ 0x12;
static volatile unsigned char RCSTA1 @ 0x13;
static volatile unsigned char RCREG1 @ 0x14;
static volatile unsigned char TXSTA1 @ 0x15;
static unsigned char TXREG1 @ 0x16;
static unsigned char SPBRG1 @ 0x17;
/* Bank 1 */
static unsigned char DDRC @ 0x110;
static volatile unsigned char PORTC @ 0x111;
static unsigned char DDRD @ 0x112;
static volatile unsigned char PORTD @ 0x113;
static unsigned char DDRE @ 0x114;
static volatile unsigned char PORTE @ 0x115;
static volatile unsigned char PIR1 @ 0x116;
static unsigned char PIE1 @ 0x117;
/* Bank 2 */
static volatile unsigned char TMR1 @ 0x210;
static volatile unsigned char TMR2 @ 0x211;
static volatile unsigned char TMR3L @ 0x212;
static volatile unsigned char TMR3H @ 0x213;
static unsigned char PR1 @ 0x214;
static unsigned char PR2 @ 0x215;
static volatile unsigned char PR3L @ 0x216;
static volatile unsigned char PR3H @ 0x217;
/* Bank 3 */
static unsigned char PW1DCL @ 0x310;
static unsigned char PW2DCL @ 0x311;
static unsigned char PW1DCH @ 0x312;
static unsigned char PW2DCH @ 0x313;
static volatile unsigned char CA2L @ 0x314;
static volatile unsigned char CA2H @ 0x315;
static unsigned char TCON1 @ 0x316;
static volatile unsigned char TCON2 @ 0x317;
/* Bank 4 */
static unsigned char PIR2 @ 0x410;
static unsigned char PIE2 @ 0x411;
static volatile unsigned char RCSTA2 @ 0x413;
static volatile unsigned char RCREG2 @ 0x414;
static volatile unsigned char TXSTA2 @ 0x415;
static volatile unsigned char TXREG2 @ 0x416;
static unsigned char SPBRG2 @ 0x417;
/* Bank 5 */
static unsigned char DDRF @ 0x510;
static volatile unsigned char PORTF @ 0x511;
static unsigned char DDRG @ 0x512;
static volatile unsigned char PORTG @ 0x513;
static volatile unsigned char ADCON0 @ 0x514;
static unsigned char ADCON1 @ 0x515;
static volatile unsigned char ADRESL @ 0x516;
static volatile unsigned char ADRESH @ 0x517;
static volatile unsigned int ADRES @ 0x516; // word version
/* Bank 6 */
static unsigned char SSPADD @ 0x610;
static volatile unsigned char SSPCON1 @ 0x611;
static volatile unsigned char SSPCON2 @ 0x612;
static volatile unsigned char SSPSTAT @ 0x613;
static volatile unsigned char SSPBUF @ 0x614;
/* Bank 7 */
static unsigned char PW3DCL @ 0x710;
static unsigned char PW3DCH @ 0x711;
static volatile unsigned char CA3L @ 0x712;
static volatile unsigned char CA3H @ 0x713;
static volatile unsigned char CA4L @ 0x714;
static volatile unsigned char CA4H @ 0x715;
static volatile unsigned char TCON3 @ 0x716;
#if defined(_17C762) || defined(_17C766)
/* Bank 8 */
static unsigned char DDRH @0x810;
static volatile unsigned char PORTH @0x811;
static unsigned char DDRJ @0x812;
static volatile unsigned char PORTJ @0x813;
#endif
/* Bank 15 */
static unsigned char TSTMD1 @ 0xF14;
static unsigned char TSTMD2 @ 0xF16;
/* ALUSTA bits */
static bit FS3 @ (unsigned)&ALUSTA*8+7;
static bit FS2 @ (unsigned)&ALUSTA*8+6;
static bit FS1 @ (unsigned)&ALUSTA*8+5;
static bit FS0 @ (unsigned)&ALUSTA*8+4;
static bit OV @ (unsigned)&ALUSTA*8+3;
static bit ZERO @ (unsigned)&ALUSTA*8+2;
static bit DC @ (unsigned)&ALUSTA*8+1;
static bit CARRY @ (unsigned)&ALUSTA*8+0;
/* T0STA bits */
static bit INTEDG @ (unsigned)&T0STA*8+7;
static bit T0SE @ (unsigned)&T0STA*8+6;
static bit T0CS @ (unsigned)&T0STA*8+5;
static bit PS3 @ (unsigned)&T0STA*8+4;
static bit PS2 @ (unsigned)&T0STA*8+3;
static bit PS1 @ (unsigned)&T0STA*8+2;
static bit PS0 @ (unsigned)&T0STA*8+1;
/* CPUSTA bits */
static volatile bit STKAV @ (unsigned)&CPUSTA*8+5;
static volatile bit GLINTD @ (unsigned)&CPUSTA*8+4;
static volatile bit TO @ (unsigned)&CPUSTA*8+3;
static volatile bit PD @ (unsigned)&CPUSTA*8+2;
static volatile bit POR @ (unsigned)&CPUSTA*8+1;
static volatile bit BOR @ (unsigned)&CPUSTA*8+0;
/* INTSTA bits */
static volatile bit PEIF @ (unsigned)&INTSTA*8+7;
static volatile bit T0CKIF @ (unsigned)&INTSTA*8+6;
static volatile bit T0IF @ (unsigned)&INTSTA*8+5;
static volatile bit INTF @ (unsigned)&INTSTA*8+4;
static bit PEIE @ (unsigned)&INTSTA*8+3;
static bit T0CKIE @ (unsigned)&INTSTA*8+2;
static bit T0IE @ (unsigned)&INTSTA*8+1;
static bit INTE @ (unsigned)&INTSTA*8+0;
/* PORTA bits */
static volatile bit RBPU @ (unsigned)&PORTA*8+7;
static volatile bit RA5 @ (unsigned)&PORTA*8+5;
static volatile bit RA4 @ (unsigned)&PORTA*8+4;
static volatile bit RA3 @ (unsigned)&PORTA*8+3;
static volatile bit RA2 @ (unsigned)&PORTA*8+2;
static volatile bit RA1 @ (unsigned)&PORTA*8+1;
static volatile bit RA0 @ (unsigned)&PORTA*8+0;
/* PORTB bits */
static volatile bit RB7 @ (unsigned)&PORTB*8+7;
static volatile bit RB6 @ (unsigned)&PORTB*8+6;
static volatile bit RB5 @ (unsigned)&PORTB*8+5;
static volatile bit RB4 @ (unsigned)&PORTB*8+4;
static volatile bit RB3 @ (unsigned)&PORTB*8+3;
static volatile bit RB2 @ (unsigned)&PORTB*8+2;
static volatile bit RB1 @ (unsigned)&PORTB*8+1;
static volatile bit RB0 @ (unsigned)&PORTB*8+0;
/* DDRB bits */
static bit DDRB7 @ (unsigned)&DDRB*8+7;
static bit DDRB6 @ (unsigned)&DDRB*8+6;
static bit DDRB5 @ (unsigned)&DDRB*8+5;
static bit DDRB4 @ (unsigned)&DDRB*8+4;
static bit DDRB3 @ (unsigned)&DDRB*8+3;
static bit DDRB2 @ (unsigned)&DDRB*8+2;
static bit DDRB1 @ (unsigned)&DDRB*8+1;
static bit DDRB0 @ (unsigned)&DDRB*8+0;
/* RCSTA1 bits */
static bit SPEN1 @ (unsigned)&RCSTA1*8+7;
static bit RX91 @ (unsigned)&RCSTA1*8+6;
static bit SREN1 @ (unsigned)&RCSTA1*8+5;
static bit CREN1 @ (unsigned)&RCSTA1*8+4;
static volatile bit FERR1 @ (unsigned)&RCSTA1*8+2;
static volatile bit OERR1 @ (unsigned)&RCSTA1*8+1;
static volatile bit RX9D1 @ (unsigned)&RCSTA1*8+0;
/* TXSTA1 bits */
static bit CSRC1 @ (unsigned)&TXSTA1*8+7;
static bit TX91 @ (unsigned)&TXSTA1*8+6;
static bit TXEN1 @ (unsigned)&TXSTA1*8+5;
static bit SYNC1 @ (unsigned)&TXSTA1*8+4;
static volatile bit TRMT1 @ (unsigned)&TXSTA1*8+1;
static bit TX9D1 @ (unsigned)&TXSTA1*8+0;
/* PORTC bits */
static volatile bit RC7 @ (unsigned)&PORTC*8+7;
static volatile bit RC6 @ (unsigned)&PORTC*8+6;
static volatile bit RC5 @ (unsigned)&PORTC*8+5;
static volatile bit RC4 @ (unsigned)&PORTC*8+4;
static volatile bit RC3 @ (unsigned)&PORTC*8+3;
static volatile bit RC2 @ (unsigned)&PORTC*8+2;
static volatile bit RC1 @ (unsigned)&PORTC*8+1;
static volatile bit RC0 @ (unsigned)&PORTC*8+0;
/* DDRC bits */
static bit DDRC7 @ (unsigned)&DDRC*8+7;
static bit DDRC6 @ (unsigned)&DDRC*8+6;
static bit DDRC5 @ (unsigned)&DDRC*8+5;
static bit DDRC4 @ (unsigned)&DDRC*8+4;
static bit DDRC3 @ (unsigned)&DDRC*8+3;
static bit DDRC2 @ (unsigned)&DDRC*8+2;
static bit DDRC1 @ (unsigned)&DDRC*8+1;
static bit DDRC0 @ (unsigned)&DDRC*8+0;
/* PORTD bits */
static volatile bit RD7 @ (unsigned)&PORTD*8+7;
static volatile bit RD6 @ (unsigned)&PORTD*8+6;
static volatile bit RD5 @ (unsigned)&PORTD*8+5;
static volatile bit RD4 @ (unsigned)&PORTD*8+4;
static volatile bit RD3 @ (unsigned)&PORTD*8+3;
static volatile bit RD2 @ (unsigned)&PORTD*8+2;
static volatile bit RD1 @ (unsigned)&PORTD*8+1;
static volatile bit RD0 @ (unsigned)&PORTD*8+0;
/* DDRD bits */
static bit DDRD7 @ (unsigned)&DDRD*8+7;
static bit DDRD6 @ (unsigned)&DDRD*8+6;
static bit DDRD5 @ (unsigned)&DDRD*8+5;
static bit DDRD4 @ (unsigned)&DDRD*8+4;
static bit DDRD3 @ (unsigned)&DDRD*8+3;
static bit DDRD2 @ (unsigned)&DDRD*8+2;
static bit DDRD1 @ (unsigned)&DDRD*8+1;
static bit DDRD0 @ (unsigned)&DDRD*8+0;
/* PORTE bits */
static volatile bit RE3 @ (unsigned)&PORTE*8+3;
static volatile bit RE2 @ (unsigned)&PORTE*8+2;
static volatile bit RE1 @ (unsigned)&PORTE*8+1;
static volatile bit RE0 @ (unsigned)&PORTE*8+0;
/* DDRE bits */
static bit DDRE3 @ (unsigned)&DDRE*8+3;
static bit DDRE2 @ (unsigned)&DDRE*8+2;
static bit DDRE1 @ (unsigned)&DDRE*8+1;
static bit DDRE0 @ (unsigned)&DDRE*8+0;
/* PIR1 bits */
static volatile bit RBIF @ (unsigned)&PIR1*8+7;
static volatile bit TMR3IF @ (unsigned)&PIR1*8+6;
static volatile bit TMR2IF @ (unsigned)&PIR1*8+5;
static volatile bit TMR1IF @ (unsigned)&PIR1*8+4;
static volatile bit CA2IF @ (unsigned)&PIR1*8+3;
static volatile bit CA1IF @ (unsigned)&PIR1*8+2;
static volatile bit TX1IF @ (unsigned)&PIR1*8+1;
static volatile bit RC1IF @ (unsigned)&PIR1*8+0;
/* PIE1 bits */
static bit RBIE @ (unsigned)&PIE1*8+7;
static bit TMR3IE @ (unsigned)&PIE1*8+6;
static bit TMR2IE @ (unsigned)&PIE1*8+5;
static bit TMR1IE @ (unsigned)&PIE1*8+4;
static bit CA2IE @ (unsigned)&PIE1*8+3;
static bit CA1IE @ (unsigned)&PIE1*8+2;
static bit TX1IE @ (unsigned)&PIE1*8+1;
static bit RC1IE @ (unsigned)&PIE1*8+0;
/* PW1DCL bits */
static bit DC1PW1 @ (unsigned)&PW1DCL*8+7;
static bit DC0PW1 @ (unsigned)&PW1DCL*8+6;
/* PW2DCL bits */
static bit DC1PW2 @ (unsigned)&PW2DCL*8+7;
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