📄 pic16f72x.h
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bit PS2 @ ((unsigned)&OPTION*8)+2;
bit PSA @ ((unsigned)&OPTION*8)+3;
bit T0SE @ ((unsigned)&OPTION*8)+4;
bit T0CS @ ((unsigned)&OPTION*8)+5;
bit INTEDG @ ((unsigned)&OPTION*8)+6;
bit RBPU @ ((unsigned)&OPTION*8)+7;
// Alternate definition for backward compatibility
bit RABPU @ ((unsigned)&OPTION*8)+7;
/* Definitions for TRISA register */
bit TRISA0 @ ((unsigned)&TRISA*8)+0;
bit TRISA1 @ ((unsigned)&TRISA*8)+1;
bit TRISA2 @ ((unsigned)&TRISA*8)+2;
bit TRISA3 @ ((unsigned)&TRISA*8)+3;
bit TRISA4 @ ((unsigned)&TRISA*8)+4;
bit TRISA5 @ ((unsigned)&TRISA*8)+5;
bit TRISA6 @ ((unsigned)&TRISA*8)+6;
bit TRISA7 @ ((unsigned)&TRISA*8)+7;
/* Definitions for TRISB register */
volatile bit TRISB0 @ ((unsigned)&TRISB*8)+0;
volatile bit TRISB1 @ ((unsigned)&TRISB*8)+1;
volatile bit TRISB2 @ ((unsigned)&TRISB*8)+2;
volatile bit TRISB3 @ ((unsigned)&TRISB*8)+3;
volatile bit TRISB4 @ ((unsigned)&TRISB*8)+4;
volatile bit TRISB5 @ ((unsigned)&TRISB*8)+5;
volatile bit TRISB6 @ ((unsigned)&TRISB*8)+6;
volatile bit TRISB7 @ ((unsigned)&TRISB*8)+7;
/* Definitions for TRISC register */
volatile bit TRISC0 @ ((unsigned)&TRISC*8)+0;
volatile bit TRISC1 @ ((unsigned)&TRISC*8)+1;
volatile bit TRISC2 @ ((unsigned)&TRISC*8)+2;
volatile bit TRISC3 @ ((unsigned)&TRISC*8)+3;
volatile bit TRISC4 @ ((unsigned)&TRISC*8)+4;
volatile bit TRISC5 @ ((unsigned)&TRISC*8)+5;
volatile bit TRISC6 @ ((unsigned)&TRISC*8)+6;
volatile bit TRISC7 @ ((unsigned)&TRISC*8)+7;
#if defined(_16F724) || defined(_16F727) ||\
defined(_16LF724) || defined(_16LF727)
/* Definitions for TRISD register */
volatile bit TRISD0 @ ((unsigned)&TRISD*8)+0;
volatile bit TRISD1 @ ((unsigned)&TRISD*8)+1;
volatile bit TRISD2 @ ((unsigned)&TRISD*8)+2;
volatile bit TRISD3 @ ((unsigned)&TRISD*8)+3;
volatile bit TRISD4 @ ((unsigned)&TRISD*8)+4;
volatile bit TRISD5 @ ((unsigned)&TRISD*8)+5;
volatile bit TRISD6 @ ((unsigned)&TRISD*8)+6;
volatile bit TRISD7 @ ((unsigned)&TRISD*8)+7;
/* Definitions for TRISE register */
volatile bit TRISE0 @ ((unsigned)&TRISE*8)+0;
volatile bit TRISE1 @ ((unsigned)&TRISE*8)+1;
volatile bit TRISE2 @ ((unsigned)&TRISE*8)+2;
#endif
volatile bit TRISE3 @ ((unsigned)&TRISE*8)+3;
/* Definitions for PIE1 register */
bit TMR1IE @ ((unsigned)&PIE1*8)+0;
bit TMR2IE @ ((unsigned)&PIE1*8)+1;
bit CCP1IE @ ((unsigned)&PIE1*8)+2;
bit SSPIE @ ((unsigned)&PIE1*8)+3;
bit TXIE @ ((unsigned)&PIE1*8)+4;
bit RCIE @ ((unsigned)&PIE1*8)+5;
bit ADIE @ ((unsigned)&PIE1*8)+6;
volatile bit TMR1GIE @ ((unsigned)&PIE1*8)+7;
/* Definitions for PIE2 register */
bit CCP2IE @ ((unsigned)&PIE2*8)+0;
/* Definitions for PCON register */
volatile bit BOR @ ((unsigned)&PCON*8)+0;
volatile bit POR @ ((unsigned)&PCON*8)+1;
/* Definitions for T1GCON register */
bit T1GSS0 @ ((unsigned)&T1GCON*8)+0;
bit T1GSS1 @ ((unsigned)&T1GCON*8)+1;
volatile bit T1GVAL @ ((unsigned)&T1GCON*8)+2;
volatile bit T1GGO @ ((unsigned)&T1GCON*8)+3;
bit T1GSPM @ ((unsigned)&T1GCON*8)+4;
bit T1GTM @ ((unsigned)&T1GCON*8)+5;
bit T1GPOL @ ((unsigned)&T1GCON*8)+6;
bit TMR1GE @ ((unsigned)&T1GCON*8)+7;
/* Definitions for OSCCON register */
bit ICSS @ ((unsigned)&OSCCON*8)+2;
bit ICSL @ ((unsigned)&OSCCON*8)+3;
bit IRCF0 @ ((unsigned)&OSCCON*8)+4;
bit IRCF1 @ ((unsigned)&OSCCON*8)+5;
/* Definitions for OSCTUNE register */
bit TUN0 @ ((unsigned)&OSCTUNE*8)+0;
bit TUN1 @ ((unsigned)&OSCTUNE*8)+1;
bit TUN2 @ ((unsigned)&OSCTUNE*8)+2;
bit TUN3 @ ((unsigned)&OSCTUNE*8)+3;
bit TUN4 @ ((unsigned)&OSCTUNE*8)+4;
bit TUN5 @ ((unsigned)&OSCTUNE*8)+5;
/* Definitions for SSPSTAT register */
volatile bit BF @ ((unsigned)&SSPSTAT*8)+0;
volatile bit UA @ ((unsigned)&SSPSTAT*8)+1;
volatile bit RW @ ((unsigned)&SSPSTAT*8)+2;
volatile bit START @ ((unsigned)&SSPSTAT*8)+3;
volatile bit STOP @ ((unsigned)&SSPSTAT*8)+4;
volatile bit DA @ ((unsigned)&SSPSTAT*8)+5;
bit CKE @ ((unsigned)&SSPSTAT*8)+6;
bit SMP @ ((unsigned)&SSPSTAT*8)+7;
/* Definitions for WPUB register */
bit WPUB0 @ ((unsigned)&WPUB*8)+0;
bit WPUB1 @ ((unsigned)&WPUB*8)+1;
bit WPUB2 @ ((unsigned)&WPUB*8)+2;
bit WPUB3 @ ((unsigned)&WPUB*8)+3;
bit WPUB4 @ ((unsigned)&WPUB*8)+4;
bit WPUB5 @ ((unsigned)&WPUB*8)+5;
bit WPUB6 @ ((unsigned)&WPUB*8)+6;
bit WPUB7 @ ((unsigned)&WPUB*8)+7;
/* Definitions for IOCB register */
bit IOCB0 @ ((unsigned)&IOCB*8)+0;
bit IOCB1 @ ((unsigned)&IOCB*8)+1;
bit IOCB2 @ ((unsigned)&IOCB*8)+2;
bit IOCB3 @ ((unsigned)&IOCB*8)+3;
bit IOCB4 @ ((unsigned)&IOCB*8)+4;
bit IOCB5 @ ((unsigned)&IOCB*8)+5;
bit IOCB6 @ ((unsigned)&IOCB*8)+6;
bit IOCB7 @ ((unsigned)&IOCB*8)+7;
/* Definitions for TXSTA register */
volatile bit TX9D @ ((unsigned)&TXSTA*8)+0;
volatile bit TRMT @ ((unsigned)&TXSTA*8)+1;
bit BRGH @ ((unsigned)&TXSTA*8)+2;
bit SYNC @ ((unsigned)&TXSTA*8)+4;
bit TXEN @ ((unsigned)&TXSTA*8)+5;
bit TX9 @ ((unsigned)&TXSTA*8)+6;
bit CSRC @ ((unsigned)&TXSTA*8)+7;
/* Definitions for SPBRG register */
bit BRG0 @ ((unsigned)&SPBRG*8)+0;
bit BRG1 @ ((unsigned)&SPBRG*8)+1;
bit BRG2 @ ((unsigned)&SPBRG*8)+2;
bit BRG3 @ ((unsigned)&SPBRG*8)+3;
bit BRG4 @ ((unsigned)&SPBRG*8)+4;
bit BRG5 @ ((unsigned)&SPBRG*8)+5;
bit BRG6 @ ((unsigned)&SPBRG*8)+6;
bit BRG7 @ ((unsigned)&SPBRG*8)+7;
/* Definitions for APFCON register */
bit CCP2SEL @ ((unsigned)&APFCON*8)+0;
bit SSSEL @ ((unsigned)&APFCON*8)+1;
/* Definitions for FVRCON register */
bit ADFVR0 @ ((unsigned)&FVRCON*8)+0;
bit ADFVR1 @ ((unsigned)&FVRCON*8)+1;
volatile bit FVREN @ ((unsigned)&FVRCON*8)+6;
volatile bit FVRRDY @ ((unsigned)&FVRCON*8)+7;
/* Definitions for ADCON1 register */
bit ADREF0 @ ((unsigned)&ADCON1*8)+0;
bit ADREF1 @ ((unsigned)&ADCON1*8)+1;
bit ADCS0 @ ((unsigned)&ADCON1*8)+4;
bit ADCS1 @ ((unsigned)&ADCON1*8)+5;
bit ADCS2 @ ((unsigned)&ADCON1*8)+6;
/* Definitions for CPSCON0 register */
bit T0XCS @ ((unsigned)&CPSCON0*8)+0;
volatile bit CPSOUT @ ((unsigned)&CPSCON0*8)+1;
bit CPSRNG0 @ ((unsigned)&CPSCON0*8)+2;
bit CPSRNG1 @ ((unsigned)&CPSCON0*8)+3;
bit CPSON @ ((unsigned)&CPSCON0*8)+7;
/* Definitions for CPSCON1 register */
bit CPSCH0 @ ((unsigned)&CPSCON1*8)+0;
bit CPSCH1 @ ((unsigned)&CPSCON1*8)+1;
bit CPSCH2 @ ((unsigned)&CPSCON1*8)+2;
bit CPSCH3 @ ((unsigned)&CPSCON1*8)+3;
/* Definitions for ANSELA register */
bit ANSA0 @ ((unsigned)&ANSELA*8)+0;
bit ANSA1 @ ((unsigned)&ANSELA*8)+1;
bit ANSA2 @ ((unsigned)&ANSELA*8)+2;
bit ANSA3 @ ((unsigned)&ANSELA*8)+3;
bit ANSA4 @ ((unsigned)&ANSELA*8)+4;
bit ANSA5 @ ((unsigned)&ANSELA*8)+5;
/* Definitions for ANSELB register */
bit ANSB0 @ ((unsigned)&ANSELB*8)+0;
bit ANSB1 @ ((unsigned)&ANSELB*8)+1;
bit ANSB2 @ ((unsigned)&ANSELB*8)+2;
bit ANSB3 @ ((unsigned)&ANSELB*8)+3;
bit ANSB4 @ ((unsigned)&ANSELB*8)+4;
bit ANSB5 @ ((unsigned)&ANSELB*8)+5;
#if defined(_16F724) || defined(_16F727) ||\
defined(_16LF724) || defined(_16LF727)
/* Definitions for ANSELD register */
bit ANSD0 @ ((unsigned)&ANSELD*8)+0;
bit ANSD1 @ ((unsigned)&ANSELD*8)+1;
bit ANSD2 @ ((unsigned)&ANSELD*8)+2;
bit ANSD3 @ ((unsigned)&ANSELD*8)+3;
bit ANSD4 @ ((unsigned)&ANSELD*8)+4;
bit ANSD5 @ ((unsigned)&ANSELD*8)+5;
bit ANSD6 @ ((unsigned)&ANSELD*8)+6;
bit ANSD7 @ ((unsigned)&ANSELD*8)+7;
/* Definitions for ANSELE register */
bit ANSE0 @ ((unsigned)&ANSELE*8)+0;
bit ANSE1 @ ((unsigned)&ANSELE*8)+1;
bit ANSE2 @ ((unsigned)&ANSELE*8)+2;
#endif
/* Definitions for PMCON1 register */
volatile bit RD @ ((unsigned)&PMCON1*8)+0;
// Configuration Mask Definitions
#define CONFIG_ADDR 0x2007
// Oscillator configurations
#define RCCLKO 0x3FFF
#define RCIO 0x3FFE
#define INTCLKO 0x3FFD
#define INTIO 0x3FFC
#define EC 0x3FFB
#define HS 0x3FFA
#define XT 0x3FF9
#define LP 0x3FF8
// Watchdog timer enable
#define WDTEN 0x3FFF
#define WDTDIS 0x3FF7
// Power up timer enable
#define PWRTEN 0x3FEF
#define PWRTDIS 0x3FFF
// MCLR pin function
#define MCLREN 0x3FFF
#define MCLRDIS 0x3FDF
// Protection of flash memory
#define PROTECT 0x3FBF
#define UNPROTECT 0x3FFF
// Brown out reset enable
#define BOREN 0x3FFF
#define BOREN_XSLP 0x3EFF
#define BORDIS 0x3CFF
// Brown out reset voltage
#define BORV25 0x3BFF
#define BORV19 0x3FFF
// INTOSC PLL enable
#define PLLEN 0x3FFF
#define PLLDIS 0x2FFF
// Debugger enable
#define DEBUGEN 0x1FFF
#define DEBUGDIS 0x3FFF
#define CONFIG_ADDR2 0x2008
// Voltage regulator capacitor enable - this setting ignored in 16LF devices
#define VCAPRA0 0x3FCF
#define VCAPRA5 0x3FDF
#define VCAPRA6 0x3FEF
#define VCAPDIS 0x3FFF
#endif
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