📄 pic16f628a.h
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//
// Register Declarations for Microchip 16F628A Processor
//
//
// This header file was automatically generated by:
//
// inc2h.pl V1.6
//
// Copyright (c) 2002, Kevin L. Pauba, All Rights Reserved
//
// SDCC is licensed under the GNU Public license (GPL) v2. Note that
// this license covers the code to the compiler and other executables,
// but explicitly does not cover any code or objects generated by sdcc.
// We have not yet decided on a license for the run time libraries, but
// it will not put any requirements on code linked against it. See:
//
// http://www.gnu.org/copyleft/gpl/html
//
// See http://sdcc.sourceforge.net/ for the latest information on sdcc.
//
//
#ifndef P16F628A_H
#define P16F628A_H
//
// Register addresses.
//
#define INDF_ADDR 0x0000
#define TMR0_ADDR 0x0001
#define PCL_ADDR 0x0002
#define STATUS_ADDR 0x0003
#define FSR_ADDR 0x0004
#define PORTA_ADDR 0x0005
#define PORTB_ADDR 0x0006
#define PCLATH_ADDR 0x000A
#define INTCON_ADDR 0x000B
#define PIR1_ADDR 0x000C
#define TMR1L_ADDR 0x000E
#define TMR1H_ADDR 0x000F
#define T1CON_ADDR 0x0010
#define TMR2_ADDR 0x0011
#define T2CON_ADDR 0x0012
#define CCPR1L_ADDR 0x0015
#define CCPR1H_ADDR 0x0016
#define CCP1CON_ADDR 0x0017
#define RCSTA_ADDR 0x0018
#define TXREG_ADDR 0x0019
#define RCREG_ADDR 0x001A
#define CMCON_ADDR 0x001F
#define OPTION_REG_ADDR 0x0081
#define TRISA_ADDR 0x0085
#define TRISB_ADDR 0x0086
#define PIE1_ADDR 0x008C
#define PCON_ADDR 0x008E
#define PR2_ADDR 0x0092
#define TXSTA_ADDR 0x0098
#define SPBRG_ADDR 0x0099
#define EEDATA_ADDR 0x009A
#define EEADR_ADDR 0x009B
#define EECON1_ADDR 0x009C
#define EECON2_ADDR 0x009D
#define VRCON_ADDR 0x009F
//
// Memory organization.
//
#pragma memmap INDF_ADDR INDF_ADDR SFR 0x000 // INDF
#pragma memmap TMR0_ADDR TMR0_ADDR SFR 0x000 // TMR0
#pragma memmap PCL_ADDR PCL_ADDR SFR 0x000 // PCL
#pragma memmap STATUS_ADDR STATUS_ADDR SFR 0x000 // STATUS
#pragma memmap FSR_ADDR FSR_ADDR SFR 0x000 // FSR
#pragma memmap PORTA_ADDR PORTA_ADDR SFR 0x000 // PORTA
#pragma memmap PORTB_ADDR PORTB_ADDR SFR 0x000 // PORTB
#pragma memmap PCLATH_ADDR PCLATH_ADDR SFR 0x000 // PCLATH
#pragma memmap INTCON_ADDR INTCON_ADDR SFR 0x000 // INTCON
#pragma memmap PIR1_ADDR PIR1_ADDR SFR 0x000 // PIR1
#pragma memmap TMR1L_ADDR TMR1L_ADDR SFR 0x000 // TMR1L
#pragma memmap TMR1H_ADDR TMR1H_ADDR SFR 0x000 // TMR1H
#pragma memmap T1CON_ADDR T1CON_ADDR SFR 0x000 // T1CON
#pragma memmap TMR2_ADDR TMR2_ADDR SFR 0x000 // TMR2
#pragma memmap T2CON_ADDR T2CON_ADDR SFR 0x000 // T2CON
#pragma memmap CCPR1L_ADDR CCPR1L_ADDR SFR 0x000 // CCPR1L
#pragma memmap CCPR1H_ADDR CCPR1H_ADDR SFR 0x000 // CCPR1H
#pragma memmap CCP1CON_ADDR CCP1CON_ADDR SFR 0x000 // CCP1CON
#pragma memmap RCSTA_ADDR RCSTA_ADDR SFR 0x000 // RCSTA
#pragma memmap TXREG_ADDR TXREG_ADDR SFR 0x000 // TXREG
#pragma memmap RCREG_ADDR RCREG_ADDR SFR 0x000 // RCREG
#pragma memmap CMCON_ADDR CMCON_ADDR SFR 0x000 // CMCON
#pragma memmap OPTION_REG_ADDR OPTION_REG_ADDR SFR 0x000 // OPTION_REG
#pragma memmap TRISA_ADDR TRISA_ADDR SFR 0x000 // TRISA
#pragma memmap TRISB_ADDR TRISB_ADDR SFR 0x000 // TRISB
#pragma memmap PIE1_ADDR PIE1_ADDR SFR 0x000 // PIE1
#pragma memmap PCON_ADDR PCON_ADDR SFR 0x000 // PCON
#pragma memmap PR2_ADDR PR2_ADDR SFR 0x000 // PR2
#pragma memmap TXSTA_ADDR TXSTA_ADDR SFR 0x000 // TXSTA
#pragma memmap SPBRG_ADDR SPBRG_ADDR SFR 0x000 // SPBRG
#pragma memmap EEDATA_ADDR EEDATA_ADDR SFR 0x000 // EEDATA
#pragma memmap EEADR_ADDR EEADR_ADDR SFR 0x000 // EEADR
#pragma memmap EECON1_ADDR EECON1_ADDR SFR 0x000 // EECON1
#pragma memmap EECON2_ADDR EECON2_ADDR SFR 0x000 // EECON2
#pragma memmap VRCON_ADDR VRCON_ADDR SFR 0x000 // VRCON
// LIST
// P16F628A.INC Standard Header File, Version 1.10 Microchip Technology, Inc.
// NOLIST
// This header file defines configurations, registers, and other useful bits of
// information for the PIC16F628A microcontroller. These names are taken to match
// the data sheets as closely as possible.
// Note that the processor must be selected before this file is
// included. The processor may be selected the following ways:
// 1. Command line switch:
// C:\ MPASM MYFILE.ASM /PIC16F628A
// 2. LIST directive in the source file
// LIST P=PIC16F628A
// 3. Processor Type entry in the MPASM full-screen interface
//==========================================================================
//
// Revision History
//
//==========================================================================
//Rev: Date: Reason:
//1.01 14 Nov 2002 Updated to reflect BOD terminology changed to BOR
//1.00 22 Aug 2002 Initial Release
//==========================================================================
//
// Verify Processor
//
//==========================================================================
// IFNDEF __16F628A
// MESSG "Processor-header file mismatch. Verify selected processor."
// ENDIF
//==========================================================================
//
// Register Definitions
//
//==========================================================================
#define W 0x0000
#define F 0x0001
//----- Register Files------------------------------------------------------
extern __data __at (INDF_ADDR) volatile char INDF;
extern __sfr __at (TMR0_ADDR) TMR0;
extern __data __at (PCL_ADDR) volatile char PCL;
extern __sfr __at (STATUS_ADDR) STATUS;
extern __sfr __at (FSR_ADDR) FSR;
extern __sfr __at (PORTA_ADDR) PORTA;
extern __sfr __at (PORTB_ADDR) PORTB;
extern __sfr __at (PCLATH_ADDR) PCLATH;
extern __sfr __at (INTCON_ADDR) INTCON;
extern __sfr __at (PIR1_ADDR) PIR1;
extern __sfr __at (TMR1L_ADDR) TMR1L;
extern __sfr __at (TMR1H_ADDR) TMR1H;
extern __sfr __at (T1CON_ADDR) T1CON;
extern __sfr __at (TMR2_ADDR) TMR2;
extern __sfr __at (T2CON_ADDR) T2CON;
extern __sfr __at (CCPR1L_ADDR) CCPR1L;
extern __sfr __at (CCPR1H_ADDR) CCPR1H;
extern __sfr __at (CCP1CON_ADDR) CCP1CON;
extern __sfr __at (RCSTA_ADDR) RCSTA;
extern __sfr __at (TXREG_ADDR) TXREG;
extern __sfr __at (RCREG_ADDR) RCREG;
extern __sfr __at (CMCON_ADDR) CMCON;
extern __sfr __at (OPTION_REG_ADDR) OPTION_REG;
extern __sfr __at (TRISA_ADDR) TRISA;
extern __sfr __at (TRISB_ADDR) TRISB;
extern __sfr __at (PIE1_ADDR) PIE1;
extern __sfr __at (PCON_ADDR) PCON;
extern __sfr __at (PR2_ADDR) PR2;
extern __sfr __at (TXSTA_ADDR) TXSTA;
extern __sfr __at (SPBRG_ADDR) SPBRG;
extern __sfr __at (EEDATA_ADDR) EEDATA;
extern __sfr __at (EEADR_ADDR) EEADR;
extern __sfr __at (EECON1_ADDR) EECON1;
extern __sfr __at (EECON2_ADDR) EECON2;
extern __sfr __at (VRCON_ADDR) VRCON;
//----- STATUS Bits --------------------------------------------------------
//----- INTCON Bits --------------------------------------------------------
//----- PIR1 Bits ----------------------------------------------------------
//----- T1CON Bits ---------------------------------------------------------
//----- T2CON Bits ---------------------------------------------------------
//----- CCP1CON Bits ---------------------------------------------------------
//----- RCSTA Bits ---------------------------------------------------------
//----- CMCON Bits ---------------------------------------------------------
//----- OPTION Bits --------------------------------------------------------
//----- PIE1 Bits ----------------------------------------------------------
//----- PCON Bits ----------------------------------------------------------
//----- TXSTA Bits ----------------------------------------------------------
//----- EECON1 Bits ---------------------------------------------------------
//----- VRCON Bits ---------------------------------------------------------
//==========================================================================
//
// RAM Definition
//
//==========================================================================
// __MAXRAM H'01FF'
// __BADRAM H'07'-H'09', H'0D', H'13'-H'14', H'1B'-H'1E'
// __BADRAM H'87'-H'89', H'8D', H'8F'-H'91', H'93'-H'97', H'9E'
// __BADRAM H'105', H'107'-H'109', H'10C'-H'11F', H'150'-H'16F'
// __BADRAM H'185', H'187'-H'189', H'18C'-H'1EF'
//==========================================================================
//
// Configuration Bits
//
//==========================================================================
#define _BODEN_ON 0x3FFF //Backwards compatability to 16F62X
#define _BODEN_OFF 0x3FBF //Backwards compatability to 16F62X
#define _BOREN_ON 0x3FFF
#define _BOREN_OFF 0x3FBF
#define _CP_ON 0x1FFF
#define _CP_OFF 0x3FFF
#define _DATA_CP_ON 0x3EFF
#define _DATA_CP_OFF 0x3FFF
#define _PWRTE_OFF 0x3FFF
#define _PWRTE_ON 0x3FF7
#define _WDT_ON 0x3FFF
#define _WDT_OFF 0x3FFB
#define _LVP_ON 0x3FFF
#define _LVP_OFF 0x3F7F
#define _MCLRE_ON 0x3FFF
#define _MCLRE_OFF 0x3FDF
#define _RC_OSC_CLKOUT 0x3FFF
#define _RC_OSC_NOCLKOUT 0x3FFE
#define _ER_OSC_CLKOUT 0x3FFF //Backwards compatability to 16F62X
#define _ER_OSC_NOCLKOUT 0x3FFE //Backwards compatability to 16F62X
#define _INTOSC_OSC_CLKOUT 0x3FFD
#define _INTOSC_OSC_NOCLKOUT 0x3FFC
#define _INTRC_OSC_CLKOUT 0x3FFD //Backwards compatability to 16F62X
#define _INTRC_OSC_NOCLKOUT 0x3FFC //Backwards compatability to 16F62X
#define _EXTCLK_OSC 0x3FEF
#define _HS_OSC 0x3FEE
#define _XT_OSC 0x3FED
#define _LP_OSC 0x3FEC
// LIST
// ----- CCP1CON bits --------------------
typedef union {
struct {
unsigned char CCP1M0:1;
unsigned char CCP1M1:1;
unsigned char CCP1M2:1;
unsigned char CCP1M3:1;
unsigned char CCP1Y:1;
unsigned char CCP1X:1;
unsigned char :1;
unsigned char :1;
};
} __CCP1CON_bits_t;
extern volatile __CCP1CON_bits_t __at(CCP1CON_ADDR) CCP1CON_bits;
#define CCP1M0 CCP1CON_bits.CCP1M0
#define CCP1M1 CCP1CON_bits.CCP1M1
#define CCP1M2 CCP1CON_bits.CCP1M2
#define CCP1M3 CCP1CON_bits.CCP1M3
#define CCP1Y CCP1CON_bits.CCP1Y
#define CCP1X CCP1CON_bits.CCP1X
// ----- CMCON bits --------------------
typedef union {
struct {
unsigned char CM0:1;
unsigned char CM1:1;
unsigned char CM2:1;
unsigned char CIS:1;
unsigned char C1INV:1;
unsigned char C2INV:1;
unsigned char C1OUT:1;
unsigned char C2OUT:1;
};
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