as16lf1828.h

picc

; HI-TECH Software PICC Assembler header file.
; Definitions based on C header file: pic16lf1828.h.

; NOTE: PICC assembler option -P is required to preprocess assembler sources. 

; Special Function Register definitions
INDF0		equ	0000h
INDF1		equ	0001h
PCL		equ	0002h
STATUS		equ	0003h
FSR0L		equ	0004h
FSR0H		equ	0005h
FSR1L		equ	0006h
FSR1H		equ	0007h
BSR		equ	0008h
WREG		equ	0009h
PCLATH		equ	000Ah
INTCON		equ	000Bh
PORTA		equ	000Ch
PORTB		equ	000Dh
PORTC		equ	000Eh
PIR1		equ	0011h
PIR2		equ	0012h
PIR3		equ	0013h
TMR0		equ	0015h
TMR1L		equ	0016h
TMR1H		equ	0017h
T1CON		equ	0018h
T1GCON		equ	0019h
TMR2		equ	001Ah
PR2		equ	001Bh
T2CON		equ	001Ch
CPSCON0		equ	001Eh
CPSCON1		equ	001Fh
TRIS_REGA		equ	008Ch
TRIS_REGB		equ	008Dh
TRIS_REGC		equ	008Eh
PIE1		equ	0091h
PIE2		equ	0092h
PIE3		equ	0093h
OPTION_REG_REG	equ	0095h
PCON		equ	0096h
WDTCON		equ	0097h
OSCTUNE		equ	0098h
OSCCON		equ	0099h
OSCSTAT		equ	009Ah
ADRESL		equ	009Bh
ADRESH		equ	009Ch
ADCON0		equ	009Dh
ADCON1		equ	009Eh
LATA		equ	010Ch
LATB		equ	010Dh
LATC		equ	010Eh
CM1CON0		equ	0111h
CM1CON1		equ	0112h
CM2CON0		equ	0113h
CM2CON1		equ	0114h
CMOUT		equ	0115h
BORCON		equ	0116h
FVRCON		equ	0117h
DACCON0		equ	0118h
DACCON1		equ	0119h
SRCON0		equ	011Ah
SRCON1		equ	011Bh
APFCON0		equ	011Dh
APFCON1		equ	011Eh
ANSELA		equ	018Ch
ANSELB		equ	018Dh
ANSELC		equ	018Eh
EEADRL		equ	0191h
EEADRH		equ	0192h
EEDATL		equ	0193h
EEDATA		equ	0193h
EEDATH		equ	0194h
EECON1		equ	0195h
EECON2		equ	0196h
RCREG		equ	0199h
TXREG		equ	019Ah
SPBRGL		equ	019Bh
SPBRG		equ	019Bh
SPBRGH		equ	019Ch
RCSTA		equ	019Dh
TXSTA		equ	019Eh
BAUDCON		equ	019Fh
WPUA		equ	020Ch
WPUB		equ	020Dh
WPUC		equ	020Eh
SSP1BUF		equ	0211h
SSPBUF		equ	0211h
SSP1ADD		equ	0212h
SSPADD		equ	0212h
SSP1MSK		equ	0213h
SSPMSK		equ	0213h
SSP1STAT	equ	0214h
SSPSTAT		equ	0214h
SSP1CON1	equ	0215h
SSPCON1		equ	0215h
SSPCON		equ	0215h
SSP1CON2	equ	0216h
SSPCON2		equ	0216h
SSP1CON3	equ	0217h
SSPCON3		equ	0217h
CCPR1L		equ	0291h
CCPR1H		equ	0292h
CCP1CON		equ	0293h
PWM1CON		equ	0294h
CCP1AS		equ	0295h
ECCP1AS		equ	0295h
PSTR1CON	equ	0296h
CCPR2L		equ	0298h
CCPR2H		equ	0299h
CCP2CON		equ	029Ah
PWM2CON		equ	029Bh
CCP2AS		equ	029Ch
PSTR2CON	equ	029Dh
CCPTMRS		equ	029Eh
CCPR3L		equ	0311h
CCPR3H		equ	0312h
CCP3CON		equ	0313h
CCPR4L		equ	0318h
CCPR4H		equ	0319h
CCP4CON		equ	031Ah
INLVLA		equ	038Ch
INLVLB		equ	038Dh
INLVLC		equ	038Eh
IOCAP		equ	0391h
IOCAN		equ	0392h
IOCAF		equ	0393h
IOCBP		equ	0394h
IOCBN		equ	0395h
IOCBF		equ	0396h
CLKRCON		equ	039Ah
MDCON		equ	039Ch
MDSRC		equ	039Dh
MDCARL		equ	039Eh
MDCARH		equ	039Fh
TMR4		equ	0415h
PR4		equ	0416h
T4CON		equ	0417h
TMR6		equ	041Ch
PR6		equ	041Dh
T6CON		equ	041Eh
STATUS_SHAD	equ	0FE4h
WREG_SHAD	equ	0FE5h
BSR_SHAD	equ	0FE6h
PCLATH_SHAD	equ	0FE7h
FSR0L_SHAD	equ	0FE8h
FSR0H_SHAD	equ	0FE9h
FSR1L_SHAD	equ	0FEAh
FSR1H_SHAD	equ	0FEBh
STKPTR		equ	0FEDh
TOSL		equ	0FEEh
TOSH		equ	0FEFh

; Bit variables associates within SFRs
#define CARRY	STATUS,0
#define DC	STATUS,1
#define ZERO	STATUS,2
#define nPD	STATUS,3
#define nTO	STATUS,4
#define BSR0	BSR,0
#define BSR1	BSR,1
#define BSR2	BSR,2
#define BSR3	BSR,3
#define BSR4	BSR,4
#define IOCIF	INTCON,0
#define INTF	INTCON,1
#define TMR0IF	INTCON,2
#define IOCIE	INTCON,3
#define INTE	INTCON,4
#define TMR0IE	INTCON,5
#define PEIE	INTCON,6
#define GIE	INTCON,7
#define T0IF	INTCON,2
#define T0IE	INTCON,5
#define RA0	PORTA,0
#define RA1	PORTA,1
#define RA2	PORTA,2
#define RA3	PORTA,3
#define RA4	PORTA,4
#define RA5	PORTA,5
#define RB4	PORTB,4
#define RB5	PORTB,5
#define RB6	PORTB,6
#define RB7	PORTB,7
#define RC0	PORTC,0
#define RC1	PORTC,1
#define RC2	PORTC,2
#define RC3	PORTC,3
#define RC4	PORTC,4
#define RC5	PORTC,5
#define RC6	PORTC,6
#define RC7	PORTC,7
#define TMR1IF	PIR1,0
#define TMR2IF	PIR1,1
#define CCP1IF	PIR1,2
#define SSP1IF	PIR1,3
#define TXIF	PIR1,4
#define RCIF	PIR1,5
#define ADIF	PIR1,6
#define TMR1GIF	PIR1,7
#define CCP2IF	PIR2,0
#define BCL1IF	PIR2,3
#define EEIF	PIR2,4
#define C1IF	PIR2,5
#define C2IF	PIR2,6
#define OSFIF	PIR2,7
#define TMR4IF	PIR3,1
#define TMR6IF	PIR3,3
#define CCP3IF	PIR3,4
#define CCP4IF	PIR3,5
#define TMR1ON	T1CON,0
#define nT1SYNC	T1CON,2
#define T1OSCEN	T1CON,3
#define T1CKPS0	T1CON,4
#define T1CKPS1	T1CON,5
#define TMR1CS0	T1CON,6
#define TMR1CS1	T1CON,7
#define T1GSS0	T1GCON,0
#define T1GSS1	T1GCON,1
#define T1GVAL	T1GCON,2
#define T1GGO	T1GCON,3
#define T1GSPM	T1GCON,4
#define T1GTM	T1GCON,5
#define T1GPOL	T1GCON,6
#define TMR1GE	T1GCON,7
#define T2CKPS0	T2CON,0
#define T2CKPS1	T2CON,1
#define TMR2ON	T2CON,2
#define T2OUTPS0	T2CON,3
#define T2OUTPS1	T2CON,4
#define T2OUTPS2	T2CON,5
#define T2OUTPS3	T2CON,6
#define T0XCS	CPSCON0,0
#define CPSOUT	CPSCON0,1
#define CPSRNG0	CPSCON0,2
#define CPSRNG1	CPSCON0,3
#define CPSRM	CPSCON0,6
#define CPSON	CPSCON0,7
#define CPSCH0	CPSCON1,0
#define CPSCH1	CPSCON1,1
#define CPSCH2	CPSCON1,2
#define CPSCH3	CPSCON1,3
#define TRIS_REGA0	TRIS_REGA,0
#define TRIS_REGA1	TRIS_REGA,1
#define TRIS_REGA2	TRIS_REGA,2
#define TRIS_REGA3	TRIS_REGA,3
#define TRIS_REGA4	TRIS_REGA,4
#define TRIS_REGA5	TRIS_REGA,5
#define TRIS_REGB4	TRIS_REGB,4
#define TRIS_REGB5	TRIS_REGB,5
#define TRIS_REGB6	TRIS_REGB,6
#define TRIS_REGB7	TRIS_REGB,7
#define TRIS_REGC0	TRIS_REGC,0
#define TRIS_REGC1	TRIS_REGC,1
#define TRIS_REGC2	TRIS_REGC,2
#define TRIS_REGC3	TRIS_REGC,3
#define TRIS_REGC4	TRIS_REGC,4
#define TRIS_REGC5	TRIS_REGC,5
#define TRIS_REGC6	TRIS_REGC,6
#define TRIS_REGC7	TRIS_REGC,7
#define TMR1IE	PIE1,0
#define TMR2IE	PIE1,1
#define CCP1IE	PIE1,2
#define SSP1IE	PIE1,3
#define TXIE	PIE1,4
#define RCIE	PIE1,5
#define ADIE	PIE1,6
#define TMR1GIE	PIE1,7
#define CCP2IE	PIE2,0
#define BCL1IE	PIE2,3
#define EEIE	PIE2,4
#define C1IE	PIE2,5
#define C2IE	PIE2,6
#define OSFIE	PIE2,7
#define TMR4IE	PIE3,1
#define TMR6IE	PIE3,3
#define CCP3IE	PIE3,4
#define CCP4IE	PIE3,5
#define PS0	OPTION_REG_REG,0
#define PS1	OPTION_REG_REG,1
#define PS2	OPTION_REG_REG,2
#define PSA	OPTION_REG_REG,3
#define TMR0SE	OPTION_REG_REG,4
#define TMR0CS	OPTION_REG_REG,5
#define INTEDG	OPTION_REG_REG,6
#define nWPUEN	OPTION_REG_REG,7
#define T0SE	OPTION_REG_REG,4
#define T0CS	OPTION_REG_REG,5
#define nBOR	PCON,0
#define nPOR	PCON,1
#define nRI	PCON,2
#define nRMCLR	PCON,3
#define STKUNF	PCON,6
#define STKOVF	PCON,7
#define SWDTEN	WDTCON,0
#define WDTPS0	WDTCON,1
#define WDTPS1	WDTCON,2
#define WDTPS2	WDTCON,3
#define WDTPS3	WDTCON,4
#define WDTPS4	WDTCON,5
#define TUN0	OSCTUNE,0
#define TUN1	OSCTUNE,1
#define TUN2	OSCTUNE,2
#define TUN3	OSCTUNE,3
#define TUN4	OSCTUNE,4
#define TUN5	OSCTUNE,5
#define SCS0	OSCCON,0
#define SCS1	OSCCON,1
#define IRCF0	OSCCON,3
#define IRCF1	OSCCON,4
#define IRCF2	OSCCON,5
#define IRCF3	OSCCON,6
#define SPLLEN	OSCCON,7
#define HFIOFS	OSCSTAT,0
#define LFIOFR	OSCSTAT,1
#define MFIOFR	OSCSTAT,2
#define HFIOFL	OSCSTAT,3
#define HFIOFR	OSCSTAT,4
#define OSTS	OSCSTAT,5
#define PLLR	OSCSTAT,6
#define T1OSCR	OSCSTAT,7
#define ADON	ADCON0,0
#define GO_nDONE	ADCON0,1
#define CHS0	ADCON0,2
#define CHS1	ADCON0,3
#define CHS2	ADCON0,4
#define CHS3	ADCON0,5
#define CHS4	ADCON0,6
#define ADGO	ADCON0,1
#define GO	ADCON0,1
#define ADPREF0	ADCON1,0
#define ADPREF1	ADCON1,1
#define ADNREF	ADCON1,2
#define ADCS0	ADCON1,4
#define ADCS1	ADCON1,5
#define ADCS2	ADCON1,6
#define ADFM	ADCON1,7
#define LATA0	LATA,0
#define LATA1	LATA,1
#define LATA2	LATA,2
#define LATA4	LATA,4
#define LATA5	LATA,5
#define LATB4	LATB,4
#define LATB5	LATB,5
#define LATB6	LATB,6
#define LATB7	LATB,7
#define LATC0	LATC,0