pic16f785.h

picc

               bit	C1IE		@ ((unsigned)&PIE1*8)+3;
               bit	C2IE		@ ((unsigned)&PIE1*8)+4;
               bit	CCP1IE		@ ((unsigned)&PIE1*8)+5;
               bit	ADIE		@ ((unsigned)&PIE1*8)+6;
               bit	EEIE		@ ((unsigned)&PIE1*8)+7;

/* Definitions for PCON register */
volatile       bit	BOR		@ ((unsigned)&PCON*8)+0;
volatile       bit	POR		@ ((unsigned)&PCON*8)+1;
               bit	SBOREN		@ ((unsigned)&PCON*8)+4;

/* Definitions for OSCCON register */
               bit	SCS		@ ((unsigned)&OSCCON*8)+0;
volatile       bit	LTS		@ ((unsigned)&OSCCON*8)+1;
volatile       bit	HTS		@ ((unsigned)&OSCCON*8)+2;
volatile       bit	OSTS		@ ((unsigned)&OSCCON*8)+3;
               bit	IRCF0		@ ((unsigned)&OSCCON*8)+4;
               bit	IRCF1		@ ((unsigned)&OSCCON*8)+5;
               bit	IRCF2		@ ((unsigned)&OSCCON*8)+6;

/* Definitions for OSCTUNE register */
               bit	TUN0		@ ((unsigned)&OSCTUNE*8)+0;
               bit	TUN1		@ ((unsigned)&OSCTUNE*8)+1;
               bit	TUN2		@ ((unsigned)&OSCTUNE*8)+2;
               bit	TUN3		@ ((unsigned)&OSCTUNE*8)+3;
               bit	TUN4		@ ((unsigned)&OSCTUNE*8)+4;

/* Definitions for ANSEL0 register */
               bit	ANS0		@ ((unsigned)&ANSEL0*8)+0;
               bit	ANS1		@ ((unsigned)&ANSEL0*8)+1;
               bit	ANS2		@ ((unsigned)&ANSEL0*8)+2;
               bit	ANS3		@ ((unsigned)&ANSEL0*8)+3;
               bit	ANS4		@ ((unsigned)&ANSEL0*8)+4;
               bit	ANS5		@ ((unsigned)&ANSEL0*8)+5;
               bit	ANS6		@ ((unsigned)&ANSEL0*8)+6;
               bit	ANS7		@ ((unsigned)&ANSEL0*8)+7;

/* Definitions for ANSEL1 register */
               bit	ANS8		@ ((unsigned)&ANSEL1*8)+0;
               bit	ANS9		@ ((unsigned)&ANSEL1*8)+1;
               bit	ANS10		@ ((unsigned)&ANSEL1*8)+2;
               bit	ANS11		@ ((unsigned)&ANSEL1*8)+3;

/* Definitions for WPUA register */
               bit	WPUA0		@ ((unsigned)&WPUA*8)+0;
               bit	WPUA1		@ ((unsigned)&WPUA*8)+1;
               bit	WPUA2		@ ((unsigned)&WPUA*8)+2;
               bit	WPUA3		@ ((unsigned)&WPUA*8)+3;
               bit	WPUA4		@ ((unsigned)&WPUA*8)+4;
               bit	WPUA5		@ ((unsigned)&WPUA*8)+5;

/* Definitions for IOCA register */
               bit	IOCA0		@ ((unsigned)&IOCA*8)+0;
               bit	IOCA1		@ ((unsigned)&IOCA*8)+1;
               bit	IOCA2		@ ((unsigned)&IOCA*8)+2;
               bit	IOCA3		@ ((unsigned)&IOCA*8)+3;
               bit	IOCA4		@ ((unsigned)&IOCA*8)+4;
               bit	IOCA5		@ ((unsigned)&IOCA*8)+5;

/* Definitions for REFCON register */
               bit	CVROE		@ ((unsigned)&REFCON*8)+1;
               bit	VROE		@ ((unsigned)&REFCON*8)+2;
               bit	VREN		@ ((unsigned)&REFCON*8)+3;
               bit	VRBB		@ ((unsigned)&REFCON*8)+4;
volatile       bit	BGST		@ ((unsigned)&REFCON*8)+5;

/* Definitions for VRCON register */
               bit	VR0		@ ((unsigned)&VRCON*8)+0;
               bit	VR1		@ ((unsigned)&VRCON*8)+1;
               bit	VR2		@ ((unsigned)&VRCON*8)+2;
               bit	VR3		@ ((unsigned)&VRCON*8)+3;
               bit	VRR		@ ((unsigned)&VRCON*8)+5;
               bit	C2VREN		@ ((unsigned)&VRCON*8)+6;
               bit	C1VREN		@ ((unsigned)&VRCON*8)+7;

/* Definitions for EECON1 register */
volatile       bit	RD		@ ((unsigned)&EECON1*8)+0;
volatile       bit	WR		@ ((unsigned)&EECON1*8)+1;
volatile       bit	WREN		@ ((unsigned)&EECON1*8)+2;
volatile       bit	WRERR		@ ((unsigned)&EECON1*8)+3;

/* Definitions for ADCON1 register */
               bit	ADCS0		@ ((unsigned)&ADCON1*8)+4;
               bit	ADCS1		@ ((unsigned)&ADCON1*8)+5;
               bit	ADCS2		@ ((unsigned)&ADCON1*8)+6;

/* Definitions for PWMCON1 register */
               bit	CMDLY0		@ ((unsigned)&PWMCON1*8)+0;
               bit	CMDLY1		@ ((unsigned)&PWMCON1*8)+1;
               bit	CMDLY2		@ ((unsigned)&PWMCON1*8)+2;
               bit	CMDLY3		@ ((unsigned)&PWMCON1*8)+3;
               bit	CMDLY4		@ ((unsigned)&PWMCON1*8)+4;
               bit	COMOD0		@ ((unsigned)&PWMCON1*8)+5;
               bit	COMOD1		@ ((unsigned)&PWMCON1*8)+6;
               bit	OVRLP		@ ((unsigned)&PWMCON1*8)+7;

/* Definitions for PWMCON0 register */
               bit	PH1EN		@ ((unsigned)&PWMCON0*8)+0;
               bit	PH2EN		@ ((unsigned)&PWMCON0*8)+1;
               bit	SYNC0		@ ((unsigned)&PWMCON0*8)+2;
               bit	SYNC1		@ ((unsigned)&PWMCON0*8)+3;
               bit	BLANK1		@ ((unsigned)&PWMCON0*8)+4;
               bit	BLANK2		@ ((unsigned)&PWMCON0*8)+5;
               bit	PASEN		@ ((unsigned)&PWMCON0*8)+6;
volatile       bit	PRSEN		@ ((unsigned)&PWMCON0*8)+7;

/* Definitions for PWMCLK register */
               bit	PER0		@ ((unsigned)&PWMCLK*8)+0;
               bit	PER1		@ ((unsigned)&PWMCLK*8)+1;
               bit	PER2		@ ((unsigned)&PWMCLK*8)+2;
               bit	PER3		@ ((unsigned)&PWMCLK*8)+3;
               bit	PER4		@ ((unsigned)&PWMCLK*8)+4;
               bit	PWMP0		@ ((unsigned)&PWMCLK*8)+5;
               bit	PWMP1		@ ((unsigned)&PWMCLK*8)+6;
volatile       bit	PWMASE		@ ((unsigned)&PWMCLK*8)+7;

/* Definitions for PWMPH1 register */
               bit	PH01		@ ((unsigned)&PWMPH1*8)+0;
               bit	PH11		@ ((unsigned)&PWMPH1*8)+1;
               bit	PH21		@ ((unsigned)&PWMPH1*8)+2;
               bit	PH31		@ ((unsigned)&PWMPH1*8)+3;
               bit	PH41		@ ((unsigned)&PWMPH1*8)+4;
               bit	C1EN1		@ ((unsigned)&PWMPH1*8)+5;
               bit	C2EN1		@ ((unsigned)&PWMPH1*8)+6;
               bit	POL1		@ ((unsigned)&PWMPH1*8)+7;

/* Definitions for PWMPH2 register */
               bit	PH02		@ ((unsigned)&PWMPH2*8)+0;
               bit	PH12		@ ((unsigned)&PWMPH2*8)+1;
               bit	PH22		@ ((unsigned)&PWMPH2*8)+2;
               bit	PH32		@ ((unsigned)&PWMPH2*8)+3;
               bit	PH42		@ ((unsigned)&PWMPH2*8)+4;
               bit	C1EN2		@ ((unsigned)&PWMPH2*8)+5;
               bit	C2EN2		@ ((unsigned)&PWMPH2*8)+6;
               bit	POL2		@ ((unsigned)&PWMPH2*8)+7;

/* Definitions for CM1CON0 register */
               bit	C1CH0		@ ((unsigned)&CM1CON0*8)+0;
               bit	C1CH1		@ ((unsigned)&CM1CON0*8)+1;
               bit	C1R		@ ((unsigned)&CM1CON0*8)+2;
               bit	C1SP		@ ((unsigned)&CM1CON0*8)+3;
               bit	C1POL		@ ((unsigned)&CM1CON0*8)+4;
               bit	C1OE		@ ((unsigned)&CM1CON0*8)+5;
volatile       bit	C1OUT		@ ((unsigned)&CM1CON0*8)+6;
               bit	C1ON		@ ((unsigned)&CM1CON0*8)+7;

/* Definitions for CM2CON0 register */
               bit	C2CH0		@ ((unsigned)&CM2CON0*8)+0;
               bit	C2CH1		@ ((unsigned)&CM2CON0*8)+1;
               bit	C2R		@ ((unsigned)&CM2CON0*8)+2;
               bit	C2SP		@ ((unsigned)&CM2CON0*8)+3;
               bit	C2POL		@ ((unsigned)&CM2CON0*8)+4;
               bit	C2OE		@ ((unsigned)&CM2CON0*8)+5;
volatile       bit	C2OUT		@ ((unsigned)&CM2CON0*8)+6;
               bit	C2ON		@ ((unsigned)&CM2CON0*8)+7;

/* Definitions for CM2CON1 register */
               bit	C2SYNC		@ ((unsigned)&CM2CON1*8)+0;
               bit	T1GSS		@ ((unsigned)&CM2CON1*8)+1;
volatile       bit	MC2OUT		@ ((unsigned)&CM2CON1*8)+6;
volatile       bit	MC1OUT		@ ((unsigned)&CM2CON1*8)+7;

/* Definitions for OPA1CON register */
               bit	OPA1ON		@ ((unsigned)&OPA1CON*8)+7;

/* Definitions for OPA2CON register */
               bit	OPA2ON		@ ((unsigned)&OPA2CON*8)+7;

// Configuration Mask Definitions
#define CONFIG_ADDR	0x2007
// Oscillator 
#define EXTCLK		0x3FFF	// External RC Clockout
#define EXTIO		0x3FFE	// External RC No Clock
#define INTCLK		0x3FFD	// Internal RC Clockout
#define INTIO		0x3FFC	// Internal RC No Clock
#define EC		0x3FFB	// EC
#define HS		0x3FFA	// HS
#define XT		0x3FF9	// XT
#define LP		0x3FF8	// LP
// Watchdog Timer 
#define WDTEN		0x3FFF	// On
#define WDTDIS		0x3FF7	// Disabled / SWDTEN control
// Power Up Timer 
#define PWRTDIS		0x3FFF	// Off
#define PWRTEN		0x3FEF	// On
// Master Clear Enable 
#define MCLREN		0x3FFF	// MCLR function is enabled
#define MCLRDIS		0x3FDF	// MCLR functions as IO
// Code Protect 
#define UNPROTECT	0x3FFF	// Code is not protected
#define CP		0x3FBF	// Code is protected
#define PROTECT		CP	//alternate
// Data EE Read Protect 
#define DUNPROTECT	0x3FFF	// Do not read protect EEPROM data
#define CPD		0x3F7F	// Read protect EEPROM data
// Brown Out Detect 
#define BORDIS		0x3CFF	// BOD and SBOREN disabled
#define SWBOREN		0x3DFF	// SBOREN controls BOR function (Software control)
#define BORXSLP		0x3EFF	// BOD enabled in run, disabled in sleep, SBOREN disabled
#define BOREN		0x3FFF	// BOD Enabled, SBOREN Disabled
// Internal External Switch Over Mode 
#define IESOEN		0x3FFF	// Enabled
#define IESODIS		0x3BFF	// Disabled
// Monitor Clock Fail-safe 
#define FCMEN		0x3FFF	// Enabled
#define FCMDIS		0x37FF	// Disabled

#endif