as12f1822.h

picc

; HI-TECH Software PICC Assembler header file.
; Definitions based on C header file: pic12f1822.h.

; NOTE: PICC assembler option -P is required to preprocess assembler sources. 

; Special Function Register definitions
INDF0		equ	0000h
INDF1		equ	0001h
PCL		equ	0002h
STATUS		equ	0003h
FSR0L		equ	0004h
FSR0H		equ	0005h
FSR1L		equ	0006h
FSR1H		equ	0007h
BSR		equ	0008h
WREG		equ	0009h
PCLATH		equ	000Ah
INTCON		equ	000Bh
PORTA		equ	000Ch
PIR1		equ	0011h
PIR2		equ	0012h
TMR0		equ	0015h
TMR1L		equ	0016h
TMR1H		equ	0017h
T1CON		equ	0018h
T1GCON		equ	0019h
TMR2		equ	001Ah
PR2		equ	001Bh
T2CON		equ	001Ch
CPSCON0		equ	001Eh
CPSCON1		equ	001Fh
TRIS_REGA		equ	008Ch
PIE1		equ	0091h
PIE2		equ	0092h
OPTION_REG_REG	equ	0095h
PCON		equ	0096h
WDTCON		equ	0097h
OSCTUNE		equ	0098h
OSCCON		equ	0099h
OSCSTAT		equ	009Ah
ADRESL		equ	009Bh
ADRESH		equ	009Ch
ADCON0		equ	009Dh
ADCON1		equ	009Eh
LATA		equ	010Ch
CM1CON0		equ	0111h
CM1CON1		equ	0112h
CMOUT		equ	0115h
BORCON		equ	0116h
FVRCON		equ	0117h
DACCON0		equ	0118h
DACCON1		equ	0119h
SRCON0		equ	011Ah
SRCON1		equ	011Bh
APFCON0		equ	011Dh
ANSELA		equ	018Ch
EEADRL		equ	0191h
EEADRH		equ	0192h
EEDATL		equ	0193h
EEDATA		equ	0193h
EEDATH		equ	0194h
EECON1		equ	0195h
EECON2		equ	0196h
RCREG		equ	0199h
TXREG		equ	019Ah
SPBRGL		equ	019Bh
SPBRG		equ	019Bh
SPBRGH		equ	019Ch
RCSTA		equ	019Dh
TXSTA		equ	019Eh
BAUDCON		equ	019Fh
WPUA		equ	020Ch
SSP1BUF		equ	0211h
SSPBUF		equ	0211h
SSP1ADD		equ	0212h
SSPADD		equ	0212h
SSP1MSK		equ	0213h
SSPMSK		equ	0213h
SSP1STAT	equ	0214h
SSPSTAT		equ	0214h
SSP1CON1	equ	0215h
SSPCON1		equ	0215h
SSPCON		equ	0215h
SSP1CON2	equ	0216h
SSPCON2		equ	0216h
SSP1CON3	equ	0217h
SSPCON3		equ	0217h
CCPR1L		equ	0291h
CCPR1H		equ	0292h
CCP1CON		equ	0293h
PWM1CON		equ	0294h
CCP1AS		equ	0295h
ECCP1AS		equ	0295h
PSTR1CON	equ	0296h
IOCAP		equ	0391h
IOCAN		equ	0392h
IOCAF		equ	0393h
CLKRCON		equ	039Ah
MDCON		equ	039Ch
MDSRC		equ	039Dh
MDCARL		equ	039Eh
MDCARH		equ	039Fh
STATUS_SHAD	equ	0FE4h
WREG_SHAD	equ	0FE5h
BSR_SHAD	equ	0FE6h
PCLATH_SHAD	equ	0FE7h
FSR0L_SHAD	equ	0FE8h
FSR0H_SHAD	equ	0FE9h
FSR1L_SHAD	equ	0FEAh
FSR1H_SHAD	equ	0FEBh
STKPTR		equ	0FEDh
TOSL		equ	0FEEh
TOSH		equ	0FEFh

; Bit variables associates within SFRs
#define CARRY	STATUS,0
#define DC	STATUS,1
#define ZERO	STATUS,2
#define nPD	STATUS,3
#define nTO	STATUS,4
#define BSR0	BSR,0
#define BSR1	BSR,1
#define BSR2	BSR,2
#define BSR3	BSR,3
#define BSR4	BSR,4
#define IOCIF	INTCON,0
#define INTF	INTCON,1
#define TMR0IF	INTCON,2
#define IOCIE	INTCON,3
#define INTE	INTCON,4
#define TMR0IE	INTCON,5
#define PEIE	INTCON,6
#define GIE	INTCON,7
#define RA0	PORTA,0
#define RA1	PORTA,1
#define RA2	PORTA,2
#define RA3	PORTA,3
#define RA4	PORTA,4
#define RA5	PORTA,5
#define TMR1IF	PIR1,0
#define TMR2IF	PIR1,1
#define CCP1IF	PIR1,2
#define SSP1IF	PIR1,3
#define TXIF	PIR1,4
#define RCIF	PIR1,5
#define ADIF	PIR1,6
#define TMR1GIF	PIR1,7
#define BCL1IF	PIR2,3
#define EEIF	PIR2,4
#define C1IF	PIR2,5
#define OSFIF	PIR2,7
#define TMR1ON	T1CON,0
#define nT1SYNC	T1CON,2
#define T1OSCEN	T1CON,3
#define T1CKPS0	T1CON,4
#define T1CKPS1	T1CON,5
#define TMR1CS0	T1CON,6
#define TMR1CS1	T1CON,7
#define T1GSS0	T1GCON,0
#define T1GSS1	T1GCON,1
#define T1GVAL	T1GCON,2
#define T1GGO	T1GCON,3
#define T1GSPM	T1GCON,4
#define T1GTM	T1GCON,5
#define T1GPOL	T1GCON,6
#define TMR1GE	T1GCON,7
#define T2CKPS0	T2CON,0
#define T2CKPS1	T2CON,1
#define TMR2ON	T2CON,2
#define T2OUTPS0	T2CON,3
#define T2OUTPS1	T2CON,4
#define T2OUTPS2	T2CON,5
#define T2OUTPS3	T2CON,6
#define T0XCS	CPSCON0,0
#define CPSOUT	CPSCON0,1
#define CPSRNG0	CPSCON0,2
#define CPSRNG1	CPSCON0,3
#define CPSON	CPSCON0,7
#define CPSCH0	CPSCON1,0
#define CPSCH1	CPSCON1,1
#define TRIS_REGA0	TRIS_REGA,0
#define TRIS_REGA1	TRIS_REGA,1
#define TRIS_REGA2	TRIS_REGA,2
#define TRIS_REGA3	TRIS_REGA,3
#define TRIS_REGA4	TRIS_REGA,4
#define TRIS_REGA5	TRIS_REGA,5
#define TMR1IE	PIE1,0
#define TMR2IE	PIE1,1
#define CCP1IE	PIE1,2
#define SSP1IE	PIE1,3
#define TXIE	PIE1,4
#define RCIE	PIE1,5
#define ADIE	PIE1,6
#define TMR1GIE	PIE1,7
#define BCL1IE	PIE2,3
#define EEIE	PIE2,4
#define C1IE	PIE2,5
#define OSFIE	PIE2,7
#define PS0	OPTION_REG_REG,0
#define PS1	OPTION_REG_REG,1
#define PS2	OPTION_REG_REG,2
#define PSA	OPTION_REG_REG,3
#define T0SE	OPTION_REG_REG,4
#define T0CS	OPTION_REG_REG,5
#define INTEDG	OPTION_REG_REG,6
#define nWPUEN	OPTION_REG_REG,7
#define nBOR	PCON,0
#define nPOR	PCON,1
#define nRI	PCON,2
#define nRMCLR	PCON,3
#define STKUNF	PCON,6
#define STKOVF	PCON,7
#define SWDTEN	WDTCON,0
#define WDTPS0	WDTCON,1
#define WDTPS1	WDTCON,2
#define WDTPS2	WDTCON,3
#define WDTPS3	WDTCON,4
#define WDTPS4	WDTCON,5
#define TUN0	OSCTUNE,0
#define TUN1	OSCTUNE,1
#define TUN2	OSCTUNE,2
#define TUN3	OSCTUNE,3
#define TUN4	OSCTUNE,4
#define TUN5	OSCTUNE,5
#define SCS0	OSCCON,0
#define SCS1	OSCCON,1
#define IRCF0	OSCCON,3
#define IRCF1	OSCCON,4
#define IRCF2	OSCCON,5
#define IRCF3	OSCCON,6
#define SPLLEN	OSCCON,7
#define HFIOFS	OSCSTAT,0
#define LFIOFR	OSCSTAT,1
#define MFIOFR	OSCSTAT,2
#define HFIOFL	OSCSTAT,3
#define HFIOFR	OSCSTAT,4
#define OSTS	OSCSTAT,5
#define PLLR	OSCSTAT,6
#define T1OSCR	OSCSTAT,7
#define ADON	ADCON0,0
#define GO_nDONE	ADCON0,1
#define CHS0	ADCON0,2
#define CHS1	ADCON0,3
#define CHS2	ADCON0,4
#define CHS3	ADCON0,5
#define CHS4	ADCON0,6
#define ADGO	ADCON0,1
#define ADPREF0	ADCON1,0
#define ADPREF1	ADCON1,1
#define ADNREF	ADCON1,2
#define ADCS0	ADCON1,4
#define ADCS1	ADCON1,5
#define ADCS2	ADCON1,6
#define ADFM	ADCON1,7
#define LATA0	LATA,0
#define LATA1	LATA,1
#define LATA2	LATA,2
#define LATA4	LATA,4
#define LATA5	LATA,5
#define C1SYNC	CM1CON0,0
#define C1HYS	CM1CON0,1
#define C1SP	CM1CON0,2
#define C1POL	CM1CON0,4
#define C1OE	CM1CON0,5
#define C1OUT	CM1CON0,6
#define C1ON	CM1CON0,7
#define C1NCH0	CM1CON1,0
#define C1PCH0	CM1CON1,4
#define C1PCH1	CM1CON1,5
#define C1INTN	CM1CON1,6
#define C1INTP	CM1CON1,7
#define MC1OUT	CMOUT,0
#define BORRDY	BORCON,0
#define SBOREN	BORCON,7
#define ADFVR0	FVRCON,0
#define ADFVR1	FVRCON,1
#define CDAFVR0	FVRCON,2
#define CDAFVR1	FVRCON,3
#define TSRNG	FVRCON,4
#define TSEN	FVRCON,5
#define FVRRDY	FVRCON,6
#define FVREN	FVRCON,7
#define DACPSS0	DACCON0,2
#define DACPSS1	DACCON0,3
#define DACOE	DACCON0,5
#define DACLPS	DACCON0,6
#define DACEN	DACCON0,7
#define DACR0	DACCON1,0
#define DACR1	DACCON1,1
#define DACR2	DACCON1,2
#define DACR3	DACCON1,3
#define DACR4	DACCON1,4
#define SRPR	SRCON0,0
#define SRPS	SRCON0,1
#define SRNQEN	SRCON0,2
#define SRQEN	SRCON0,3
#define SRCLK0	SRCON0,4
#define SRCLK1	SRCON0,5
#define SRCLK2	SRCON0,6
#define SRLEN	SRCON0,7
#define SRRC1E	SRCON1,0
#define SRRCKE	SRCON1,2
#define SRRPE	SRCON1,3
#define SRSC1E	SRCON1,4
#define SRSCKE	SRCON1,6
#define SRSPE	SRCON1,7
#define CCP1SEL	APFCON0,0
#define P1BSEL	APFCON0,1
#define TXCKSEL	APFCON0,2
#define T1GSEL	APFCON0,3
#define SS1SEL	APFCON0,5
#define SDO1SEL	APFCON0,6
#define RXDTSEL	APFCON0,7
#define ANSA0	ANSELA,0
#define ANSA1	ANSELA,1
#define ANSA2	ANSELA,2
#define ANSA4	ANSELA,4
#define RD	EECON1,0
#define WR	EECON1,1
#define WREN	EECON1,2
#define WRERR	EECON1,3
#define FREE	EECON1,4
#define LWLO	EECON1,5
#define CFGS	EECON1,6
#define EEPGD	EECON1,7
#define RX9D	RCSTA,0
#define OERR	RCSTA,1
#define FERR	RCSTA,2
#define ADDEN	RCSTA,3
#define CREN	RCSTA,4
#define SREN	RCSTA,5
#define RX9	RCSTA,6
#define SPEN	RCSTA,7
#define TX9D	TXSTA,0
#define TRMT	TXSTA,1
#define BRGH	TXSTA,2
#define SENDB	TXSTA,3
#define SYNC	TXSTA,4
#define TXEN	TXSTA,5
#define TX9	TXSTA,6
#define CSRC	TXSTA,7
#define ABDEN	BAUDCON,0
#define WUE	BAUDCON,1
#define BRG16	BAUDCON,3
#define SCKP	BAUDCON,4
#define RCIDL	BAUDCON,6
#define ABDOVF	BAUDCON,7
#define WPUA0	WPUA,0
#define WPUA1	WPUA,1
#define WPUA2	WPUA,2
#define WPUA3	WPUA,3
#define WPUA4	WPUA,4
#define WPUA5	WPUA,5
#define BF	SSP1STAT,0
#define UA	SSP1STAT,1
#define R_nW	SSP1STAT,2
#define S	SSP1STAT,3
#define P	SSP1STAT,4
#define D_nA	SSP1STAT,5
#define CKE	SSP1STAT,6
#define SMP	SSP1STAT,7
#define SSPM0	SSP1CON1,0
#define SSPM1	SSP1CON1,1
#define SSPM2	SSP1CON1,2
#define SSPM3	SSP1CON1,3
#define CKP	SSP1CON1,4
#define SSPEN	SSP1CON1,5
#define SSPOV	SSP1CON1,6
#define WCOL	SSP1CON1,7
#define SEN	SSP1CON2,0
#define RSEN	SSP1CON2,1
#define PEN	SSP1CON2,2
#define RCEN	SSP1CON2,3
#define ACKEN	SSP1CON2,4
#define ACKDT	SSP1CON2,5
#define ACKSTAT	SSP1CON2,6
#define GCEN	SSP1CON2,7
#define DHEN	SSP1CON3,0
#define AHEN	SSP1CON3,1
#define SBCDE	SSP1CON3,2
#define SDAHT	SSP1CON3,3
#define BOEN	SSP1CON3,4
#define SCIE	SSP1CON3,5
#define PCIE	SSP1CON3,6
#define ACKTIM	SSP1CON3,7
#define CCP1M0	CCP1CON,0
#define CCP1M1	CCP1CON,1
#define CCP1M2	CCP1CON,2
#define CCP1M3	CCP1CON,3
#define DC1B0	CCP1CON,4
#define DC1B1	CCP1CON,5
#define P1M0	CCP1CON,6
#define P1M1	CCP1CON,7
#define P1DC0	PWM1CON,0
#define P1DC1	PWM1CON,1
#define P1DC2	PWM1CON,2
#define P1DC3	PWM1CON,3
#define P1DC4	PWM1CON,4
#define P1DC5	PWM1CON,5
#define P1DC6	PWM1CON,6
#define P1RSEN	PWM1CON,7
#define PSS1BD0	CCP1AS,0
#define PSS1BD1	CCP1AS,1
#define PSS1AC0	CCP1AS,2
#define PSS1AC1	CCP1AS,3
#define CCP1AS0	CCP1AS,4
#define CCP1AS1	CCP1AS,5
#define CCP1AS2	CCP1AS,6
#define CCP1ASE	CCP1AS,7
#define STR1A	PSTR1CON,0
#define STR1B	PSTR1CON,1
#define STR1C	PSTR1CON,2
#define STR1D	PSTR1CON,3
#define STR1SYNC	PSTR1CON,4
#define IOCAP0	IOCAP,0
#define IOCAP1	IOCAP,1
#define IOCAP2	IOCAP,2
#define IOCAP3	IOCAP,3
#define IOCAP4	IOCAP,4
#define IOCAP5	IOCAP,5
#define IOCAN0	IOCAN,0
#define IOCAN1	IOCAN,1
#define IOCAN2	IOCAN,2
#define IOCAN3	IOCAN,3
#define IOCAN4	IOCAN,4
#define IOCAN5	IOCAN,5
#define IOCAF0	IOCAF,0
#define IOCAF1	IOCAF,1
#define IOCAF2	IOCAF,2
#define IOCAF3	IOCAF,3
#define IOCAF4	IOCAF,4
#define IOCAF5	IOCAF,5
#define CLKRDIV0	CLKRCON,0
#define CLKRDIV1	CLKRCON,1
#define CLKRDIV2	CLKRCON,2
#define CLKRDC0	CLKRCON,3
#define CLKRDC1	CLKRCON,4
#define CLKRSLR	CLKRCON,5
#define CLKROE	CLKRCON,6
#define CLKREN	CLKRCON,7
#define MDBIT	MDCON,0
#define MDOPOL	MDCON,4
#define MDSLR	MDCON,5
#define MDOE	MDCON,6
#define MDEN	MDCON,7
#define MDMS0	MDSRC,0
#define MDMS1	MDSRC,1
#define MDMS2	MDSRC,2
#define MDMS3	MDSRC,3
#define MDMSODIS	MDSRC,7
#define C_SHAD	STATUS_SHAD,0
#define DC_SHAD	STATUS_SHAD,1
#define Z_SHAD	STATUS_SHAD,2