pic16f1827.h

picc

volatile bit SRRC1E              @ ((unsigned)&SRCON1*8)+0;
// SR Latch C2 Reset Enable bit
volatile bit SRRC2E              @ ((unsigned)&SRCON1*8)+1;
// SR Latch Reset Clock Enable bit
volatile bit SRRCKE              @ ((unsigned)&SRCON1*8)+2;
// SR Latch Peripheral Reset Enable bit
volatile bit SRRPE               @ ((unsigned)&SRCON1*8)+3;
// SR Latch C1 Set Enable bit
volatile bit SRSC1E              @ ((unsigned)&SRCON1*8)+4;
// SR Latch C2 Set Enable bit
volatile bit SRSC2E              @ ((unsigned)&SRCON1*8)+5;
// SR Latch Set Clock Enable bit
volatile bit SRSCKE              @ ((unsigned)&SRCON1*8)+6;
// SR Latch Peripheral Set Enable bit
volatile bit SRSPE               @ ((unsigned)&SRCON1*8)+7;
#ifndef _LIB_BUILD
union {
    struct {
        volatile unsigned SRRC1E              : 1;
        volatile unsigned SRRC2E              : 1;
        volatile unsigned SRRCKE              : 1;
        volatile unsigned SRRPE               : 1;
        volatile unsigned SRSC1E              : 1;
        volatile unsigned SRSC2E              : 1;
        volatile unsigned SRSCKE              : 1;
        volatile unsigned SRSPE               : 1;
    };
} SRCON1bits @ 0x11B;
#endif

// Register: APFCON0
// Alternate Pin Function Control Register
volatile unsigned char           APFCON0             @ 0x11D;
// bit and bitfield definitions
// CCP2 Input/Output Pin Selection
volatile bit CCP1SEL             @ ((unsigned)&APFCON0*8)+0;
// SS Input Pin Selection
volatile bit P1CSEL              @ ((unsigned)&APFCON0*8)+1;
// Comparator 2 Output Pin Selection
volatile bit P1DSEL              @ ((unsigned)&APFCON0*8)+2;
// SR Latch nQ Output Pin Selection
volatile bit CCP2SEL             @ ((unsigned)&APFCON0*8)+3;
// CCP2 PWM B Output Pin Selection
volatile bit P2BSEL              @ ((unsigned)&APFCON0*8)+4;
// Timer1 Gate Input Pin Selection
volatile bit SS1SEL              @ ((unsigned)&APFCON0*8)+5;
// CCP3 Input/Output Pin Selection
volatile bit SDO1SEL             @ ((unsigned)&APFCON0*8)+6;
volatile bit RXDTSEL             @ ((unsigned)&APFCON0*8)+7;
#ifndef _LIB_BUILD
union {
    struct {
        volatile unsigned CCP1SEL             : 1;
        volatile unsigned P1CSEL              : 1;
        volatile unsigned P1DSEL              : 1;
        volatile unsigned CCP2SEL             : 1;
        volatile unsigned P2BSEL              : 1;
        volatile unsigned SS1SEL              : 1;
        volatile unsigned SDO1SEL             : 1;
        volatile unsigned RXDTSEL             : 1;
    };
} APFCON0bits @ 0x11D;
#endif

// Register: APFCON1
volatile unsigned char           APFCON1             @ 0x11E;
// bit and bitfield definitions
volatile bit TXCKSEL             @ ((unsigned)&APFCON1*8)+0;
#ifndef _LIB_BUILD
union {
    struct {
        volatile unsigned TXCKSEL             : 1;
    };
} APFCON1bits @ 0x11E;
#endif

//
// Special function register definitions: Bank 3
//

// Register: ANSELA
volatile unsigned char           ANSELA              @ 0x18C;
// bit and bitfield definitions
volatile bit ANSA0               @ ((unsigned)&ANSELA*8)+0;
volatile bit ANSA1               @ ((unsigned)&ANSELA*8)+1;
volatile bit ANSA2               @ ((unsigned)&ANSELA*8)+2;
volatile bit ANSA3               @ ((unsigned)&ANSELA*8)+3;
volatile bit ANSA4               @ ((unsigned)&ANSELA*8)+4;
#ifndef _LIB_BUILD
union {
    struct {
        volatile unsigned ANSA0               : 1;
        volatile unsigned ANSA1               : 1;
        volatile unsigned ANSA2               : 1;
        volatile unsigned ANSA3               : 1;
        volatile unsigned ANSA4               : 1;
        volatile unsigned                     : 1;
        volatile unsigned : 1;
        volatile unsigned : 1;
    };
    struct {
        volatile unsigned ANSELA              : 5;
        volatile unsigned : 1;
    };
} ANSELAbits @ 0x18C;
#endif

// Register: ANSELB
volatile unsigned char           ANSELB              @ 0x18D;
// bit and bitfield definitions
volatile bit ANSB1               @ ((unsigned)&ANSELB*8)+1;
volatile bit ANSB2               @ ((unsigned)&ANSELB*8)+2;
volatile bit ANSB3               @ ((unsigned)&ANSELB*8)+3;
volatile bit ANSB4               @ ((unsigned)&ANSELB*8)+4;
volatile bit ANSB5               @ ((unsigned)&ANSELB*8)+5;
volatile bit ANSB6               @ ((unsigned)&ANSELB*8)+6;
volatile bit ANSB7               @ ((unsigned)&ANSELB*8)+7;
#ifndef _LIB_BUILD
union {
    struct {
        volatile unsigned                     : 1;
        volatile unsigned ANSB1               : 1;
        volatile unsigned ANSB2               : 1;
        volatile unsigned ANSB3               : 1;
        volatile unsigned ANSB4               : 1;
        volatile unsigned ANSB5               : 1;
        volatile unsigned ANSB6               : 1;
        volatile unsigned ANSB7               : 1;
    };
} ANSELBbits @ 0x18D;
#endif
// bit and bitfield definitions

// Register: EEADRL
volatile unsigned char           EEADRL              @ 0x191;
// bit and bitfield definitions

// Register: EEADRH
volatile unsigned char           EEADRH              @ 0x192;
// bit and bitfield definitions
#ifndef _LIB_BUILD
union {
    struct {
        volatile unsigned EEADRH              : 7;
    };
} EEADRHbits @ 0x192;
#endif

// Register: EEADR
volatile unsigned int            EEADR               @ 0x191;
// bit and bitfield definitions

// Register: EEDATL
volatile unsigned char           EEDATL              @ 0x193;
volatile unsigned char           EEDATA              @ 0x193;
// bit and bitfield definitions

// Register: EEDATH
volatile unsigned char           EEDATH              @ 0x194;
// bit and bitfield definitions
#ifndef _LIB_BUILD
union {
    struct {
        volatile unsigned EEDATH              : 6;
    };
} EEDATHbits @ 0x194;
#endif

// Register: EEDAT
volatile unsigned int            EEDAT               @ 0x193;

// Register: EECON1
volatile unsigned char           EECON1              @ 0x195;
// bit and bitfield definitions
// Read Control bit
volatile bit RD                  @ ((unsigned)&EECON1*8)+0;
// Write Control bit
volatile bit WR                  @ ((unsigned)&EECON1*8)+1;
// Program/Erase Enable bit
volatile bit WREN                @ ((unsigned)&EECON1*8)+2;
// Sequence Error Flag bit
volatile bit WRERR               @ ((unsigned)&EECON1*8)+3;
// Program FLASH Erase Enable bit
volatile bit FREE                @ ((unsigned)&EECON1*8)+4;
// Load Write Latches Only bit
volatile bit LWLO                @ ((unsigned)&EECON1*8)+5;
// FLASH Program / Data EEPROM or Configuration Select bit
volatile bit CFGS                @ ((unsigned)&EECON1*8)+6;
// FLASH Program / Data EEPROM Memory Select bit
volatile bit EEPGD               @ ((unsigned)&EECON1*8)+7;
#ifndef _LIB_BUILD
union {
    struct {
        volatile unsigned RD                  : 1;
        volatile unsigned WR                  : 1;
        volatile unsigned WREN                : 1;
        volatile unsigned WRERR               : 1;
        volatile unsigned FREE                : 1;
        volatile unsigned LWLO                : 1;
        volatile unsigned CFGS                : 1;
        volatile unsigned EEPGD               : 1;
    };
} EECON1bits @ 0x195;
#endif

// Register: EECON2
volatile unsigned char           EECON2              @ 0x196;
// bit and bitfield definitions

// Register: RCREG
volatile unsigned char           RCREG               @ 0x199;
// bit and bitfield definitions

// Register: TXREG
volatile unsigned char           TXREG               @ 0x19A;
// bit and bitfield definitions

// Register: SPBRGL
volatile unsigned char           SPBRGL              @ 0x19B;
volatile unsigned char           SPBRG               @ 0x19B;
// bit and bitfield definitions

// Register: SPBRGH
volatile unsigned char           SPBRGH              @ 0x19C;
// bit and bitfield definitions

// Register: RCSTA
// Receive Status and Control Register
volatile unsigned char           RCSTA               @ 0x19D;
// bit and bitfield definitions
// 9th bit of received data (can be parity bit)
volatile bit RX9D                @ ((unsigned)&RCSTA*8)+0;
// Overrun Error bit
volatile bit OERR                @ ((unsigned)&RCSTA*8)+1;
// Framing Error bit
volatile bit FERR                @ ((unsigned)&RCSTA*8)+2;
// Address Detect Enable bit
volatile bit ADDEN               @ ((unsigned)&RCSTA*8)+3;
// Continuous Receive Enable bit
volatile bit CREN                @ ((unsigned)&RCSTA*8)+4;
// Single Receive Enable bit
volatile bit SREN                @ ((unsigned)&RCSTA*8)+5;
// 9-bit Receive Enable bit
volatile bit RX9                 @ ((unsigned)&RCSTA*8)+6;
// Serial Port Enable bit
volatile bit SPEN                @ ((unsigned)&RCSTA*8)+7;
#ifndef _LIB_BUILD
union {
    struct {
        volatile unsigned RX9D                : 1;
        volatile unsigned OERR                : 1;
        volatile unsigned FERR                : 1;
        volatile unsigned ADDEN               : 1;
        volatile unsigned CREN                : 1;
        volatile unsigned SREN                : 1;
        volatile unsigned RX9                 : 1;
        volatile unsigned SPEN                : 1;
    };
} RCSTAbits @ 0x19D;
#endif

// Register: TXSTA
// Transmit Status and Control Register
volatile unsigned char           TXSTA               @ 0x19E;
// bit and bitfield definitions
// 9th bit of transmit data; can be used as parity bit
volatile bit TX9D                @ ((unsigned)&TXSTA*8)+0;
// Transmit Operation Idle Status bit
volatile bit TRMT                @ ((unsigned)&TXSTA*8)+1;
// High Baud Rate Select bit
volatile bit BRGH                @ ((unsigned)&TXSTA*8)+2;
// Send BREAK character bit
volatile bit SENDB               @ ((unsigned)&TXSTA*8)+3;
// USART Mode Select bit
volatile bit SYNC                @ ((unsigned)&TXSTA*8)+4;
// Transmit Enable bit
volatile bit TXEN                @ ((unsigned)&TXSTA*8)+5;
// 9-bit Transmit Enable bit
volatile bit TX9                 @ ((unsigned)&TXSTA*8)+6;
// Clock Source Select bit
volatile bit CSRC                @ ((unsigned)&TXSTA*8)+7;
#ifndef _LIB_BUILD
union {
    struct {
        volatile unsigned TX9D                : 1;
        volatile unsigned TRMT                : 1;
        volatile unsigned BRGH                : 1;
        volatile unsigned SENDB               : 1;
        volatile unsigned SYNC                : 1;
        volatile unsigned TXEN                : 1;
        volatile unsigned TX9                 : 1;
        volatile unsigned CSRC                : 1;
    };
} TXSTAbits @ 0x19E;
#endif

// Register: BAUDCON
// Baud Rate Control Register
volatile unsigned char           BAUDCON             @ 0x19F;
// bit and bitfield definitions
// Auto-Baud Detect Enable bit
volatile bit ABDEN               @ ((unsigned)&BAUDCON*8)+0;
// Wake-Up Enable bit
volatile bit WUE                 @ ((unsigned)&BAUDCON*8)+1;
// 16-bit Baud Rate Register enable bit
volatile bit BRG16               @ ((unsigned)&BAUDCON*8)+3;
// Clock/Transmit Polarity Select bit
volatile bit SCKP                @ ((unsigned)&BAUDCON*8)+4;
// Receive Operation Idle Status bit
volatile bit RCIDL               @ ((unsigned)&BAUDCON*8)+6;
// BRG Rollover Status bit
volatile bit ABDOVF              @ ((unsigned)&BAUDCON*8)+7;
#ifndef _LIB_BUILD
union {
    struct {
        volatile unsigned ABDEN               : 1;
        volatile unsigned WUE                 : 1;
        volatile unsigned                     : 1;
        volatile unsigned BRG16               : 1;
        volatile unsigned SCKP                : 1;
        volatile unsigned : 1;
        volatile unsigned RCIDL               : 1;
        volatile unsigned ABDOVF              : 1;
    };
} BAUDCONbits @ 0x19F;
#endif

//
// Special function register definitions: Bank 4
//

// Register: WPUA
volatile unsigned char           WPUA                @ 0x20C;
// bit and bitfield definitions
volatile bit WPUA5               @ ((unsigned)&WPUA*8)+5;
#ifndef _LIB_BUILD
union {
    struct {
        volatile unsigned                     : 5;
        volatile unsigned WPUA5               : 1;
    };
} WPUAbits @ 0x20C;
#endif

// Register: WPUB
volatile unsigned char           WPUB                @