📄 pic1677x.h
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/* TXSTA bits */
#if defined(_16C773) || defined(_16C774) || defined(_16C745) || defined(_16C765)
volatile bit CSRC @ (unsigned)&TXSTA*8+7;
volatile bit TX9 @ (unsigned)&TXSTA*8+6;
volatile bit TXEN @ (unsigned)&TXSTA*8+5;
volatile bit SYNC @ (unsigned)&TXSTA*8+4;
volatile bit BRGH @ (unsigned)&TXSTA*8+2;
volatile bit TRMT @ (unsigned)&TXSTA*8+1;
volatile bit TX9D @ (unsigned)&TXSTA*8+0;
#endif
/* REFCON bits */
#if !defined(_16C745) && !defined(_16C765)
volatile bit VRHEN @ (unsigned)&REFCON*8+7;
volatile bit VRLEN @ (unsigned)&REFCON*8+6;
volatile bit VRHOEN @ (unsigned)&REFCON*8+5;
volatile bit VRLOEN @ (unsigned)&REFCON*8+4;
/* LVDCON bits */
volatile bit BGST @ (unsigned)&LVDCON*8+5;
volatile bit LVDEN @ (unsigned)&LVDCON*8+4;
volatile bit LV3 @ (unsigned)&LVDCON*8+3;
volatile bit LV2 @ (unsigned)&LVDCON*8+2;
volatile bit LV1 @ (unsigned)&LVDCON*8+1;
volatile bit LV0 @ (unsigned)&LVDCON*8+0;
#endif
/* ANSEL bits */
#if defined(_16C770) || defined(_16C771) || defined(_16C717)
bit ANSEL5 @ (unsigned)&ANSEL*8+5;
bit ANSEL4 @ (unsigned)&ANSEL*8+4;
bit ANSEL3 @ (unsigned)&ANSEL*8+3;
bit ANSEL2 @ (unsigned)&ANSEL*8+2;
bit ANSEL1 @ (unsigned)&ANSEL*8+1;
bit ANSEL0 @ (unsigned)&ANSEL*8+0;
#endif
/* ADRESL bits */
#if !defined(_16C745) && !defined(_16C765)
bit ADRESL7 @ (unsigned)&ADRESL*8+7;
bit ADRESL6 @ (unsigned)&ADRESL*8+6;
bit ADRESL5 @ (unsigned)&ADRESL*8+5;
bit ADRESL4 @ (unsigned)&ADRESL*8+4;
bit ADRESL3 @ (unsigned)&ADRESL*8+3;
bit ADRESL2 @ (unsigned)&ADRESL*8+2;
bit ADRESL1 @ (unsigned)&ADRESL*8+1;
bit ADRESL0 @ (unsigned)&ADRESL*8+0;
#endif
/* ADCON1 bits */
#if !defined(_16C745) && !defined(_16C765)
volatile bit ADFM @ (unsigned)&ADCON1*8+7;
volatile bit VCFG2 @ (unsigned)&ADCON1*8+6;
volatile bit VCFG1 @ (unsigned)&ADCON1*8+5;
volatile bit VCFG0 @ (unsigned)&ADCON1*8+4;
#endif
#if defined(_16C773) || defined(_16C774) || defined(_16C745) || defined(_16C765)
#if !defined(_16C774) && !defined(_16C765)
volatile bit PCFG3 @ (unsigned)&ADCON1*8+3;
#endif
volatile bit PCFG2 @ (unsigned)&ADCON1*8+2;
volatile bit PCFG1 @ (unsigned)&ADCON1*8+1;
volatile bit PCFG0 @ (unsigned)&ADCON1*8+0;
#endif
#if defined(_16C770) || defined(_16C771) || defined(_16C717)
/* PMDATL bits */
bit PMDATL7 @ (unsigned)&PMDATL*8+7;
bit PMDATL6 @ (unsigned)&PMDATL*8+6;
bit PMDATL5 @ (unsigned)&PMDATL*8+5;
bit PMDATL4 @ (unsigned)&PMDATL*8+4;
bit PMDATL3 @ (unsigned)&PMDATL*8+3;
bit PMDATL2 @ (unsigned)&PMDATL*8+2;
bit PMDATL1 @ (unsigned)&PMDATL*8+1;
bit PMDATL0 @ (unsigned)&PMDATL*8+0;
/* PMADRL bits */
bit PMADRL7 @ (unsigned)&PMADRL*8+7;
bit PMADRL6 @ (unsigned)&PMADRL*8+6;
bit PMADRL5 @ (unsigned)&PMADRL*8+5;
bit PMADRL4 @ (unsigned)&PMADRL*8+4;
bit PMADRL3 @ (unsigned)&PMADRL*8+3;
bit PMADRL2 @ (unsigned)&PMADRL*8+2;
bit PMADRL1 @ (unsigned)&PMADRL*8+1;
bit PMADRL0 @ (unsigned)&PMADRL*8+0;
/* PMDATH bits */
bit PMDATH5 @ (unsigned)&PMDATH*8+5;
bit PMDATH4 @ (unsigned)&PMDATH*8+4;
bit PMDATH3 @ (unsigned)&PMDATH*8+3;
bit PMDATH2 @ (unsigned)&PMDATH*8+2;
bit PMDATH1 @ (unsigned)&PMDATH*8+1;
bit PMDATH0 @ (unsigned)&PMDATH*8+0;
/* PMADRH bits */
bit PMADRH3 @ (unsigned)&PMADRH*8+3;
bit PMADRH2 @ (unsigned)&PMADRH*8+2;
bit PMADRH1 @ (unsigned)&PMADRH*8+1;
bit PMADRH0 @ (unsigned)&PMADRH*8+0;
#endif
/* USB bits */
#if defined(_16C745) || defined(_16C765)
volatile bit STALL @ (unsigned)&UIR*8+5;
volatile bit UIDLE @ (unsigned)&UIR*8+4;
volatile bit TOK_DONE @ (unsigned)&UIR*8+3;
volatile bit ACTIVITY @ (unsigned)&UIR*8+2;
volatile bit UERR @ (unsigned)&UIR*8+1;
volatile bit USB_RST @ (unsigned)&UIR*8+0;
volatile bit STALL_E @ (unsigned)&UIE*8+5;
volatile bit UIDLE_E @ (unsigned)&UIE*8+4;
volatile bit TOK_DONE_E @ (unsigned)&UIE*8+3;
volatile bit ACTIVITY_E @ (unsigned)&UIE*8+2;
volatile bit UERR_E @ (unsigned)&UIE*8+1;
volatile bit USB_RST_E @ (unsigned)&UIE*8+0;
volatile bit BTS_ERR @ (unsigned)&UEIR*8+7;
volatile bit OWN_ERR @ (unsigned)&UEIR*8+6;
volatile bit WRT_ERR @ (unsigned)&UEIR*8+5;
volatile bit BTO_ERR @ (unsigned)&UEIR*8+4;
volatile bit DFN8 @ (unsigned)&UEIR*8+3;
volatile bit CRC16 @ (unsigned)&UEIR*8+2;
volatile bit CRC5 @ (unsigned)&UEIR*8+1;
volatile bit PID_ERR @ (unsigned)&UEIR*8+0;
volatile bit BTS_ERR_E @ (unsigned)&UEIE*8+7;
volatile bit OWN_ERR_E @ (unsigned)&UEIE*8+6;
volatile bit WRT_ERR_E @ (unsigned)&UEIE*8+5;
volatile bit BTO_ERR_E @ (unsigned)&UEIE*8+4;
volatile bit DFN8_E @ (unsigned)&UEIE*8+3;
volatile bit CRC16_E @ (unsigned)&UEIE*8+2;
volatile bit CRC5_E @ (unsigned)&UEIE*8+1;
volatile bit PID_ERR_E @ (unsigned)&UEIE*8+0;
volatile bit ENDP1 @ (unsigned)&USTAT*8+4;
volatile bit ENDP0 @ (unsigned)&USTAT*8+3;
volatile bit IN @ (unsigned)&USTAT*8+2;
volatile bit SEO @ (unsigned)&UCTRL*8+5;
volatile bit PKT_DIS @ (unsigned)&UCTRL*8+4;
volatile bit DEV_ATT @ (unsigned)&UCTRL*8+3;
volatile bit RESUME @ (unsigned)&UCTRL*8+2;
volatile bit SUSPND @ (unsigned)&UCTRL*8+1;
volatile bit ADDR6 @ (unsigned)&UADDR*8+6;
volatile bit ADDR5 @ (unsigned)&UADDR*8+5;
volatile bit ADDR4 @ (unsigned)&UADDR*8+4;
volatile bit ADDR3 @ (unsigned)&UADDR*8+3;
volatile bit ADDR2 @ (unsigned)&UADDR*8+2;
volatile bit ADDR1 @ (unsigned)&UADDR*8+1;
volatile bit ADDR0 @ (unsigned)&UADDR*8+0;
volatile bit SWSTAT7 @ (unsigned)&USWSTAT*8+7;
volatile bit SWSTAT6 @ (unsigned)&USWSTAT*8+6;
volatile bit SWSTAT5 @ (unsigned)&USWSTAT*8+5;
volatile bit SWSTAT4 @ (unsigned)&USWSTAT*8+4;
volatile bit SWSTAT3 @ (unsigned)&USWSTAT*8+3;
volatile bit SWSTAT2 @ (unsigned)&USWSTAT*8+2;
volatile bit SWSTAT1 @ (unsigned)&USWSTAT*8+1;
volatile bit SWSTAT0 @ (unsigned)&USWSTAT*8+0;
volatile bit EP_CTL_DIS0 @ (unsigned)&UEP0*8+3;
volatile bit EP_OUT_EN0 @ (unsigned)&UEP0*8+2;
volatile bit EP_IN_EN0 @ (unsigned)&UEP0*8+1;
volatile bit EP_STALL0 @ (unsigned)&UEP0*8+0;
volatile bit EP_CTL_DIS1 @ (unsigned)&UEP1*8+3;
volatile bit EP_OUT_EN1 @ (unsigned)&UEP1*8+2;
volatile bit EP_IN_EN1 @ (unsigned)&UEP1*8+1;
volatile bit EP_STALL1 @ (unsigned)&UEP1*8+0;
volatile bit EP_CTL_DIS2 @ (unsigned)&UEP2*8+3;
volatile bit EP_OUT_EN2 @ (unsigned)&UEP2*8+2;
volatile bit EP_IN_EN2 @ (unsigned)&UEP2*8+1;
volatile bit EP_STALL2 @ (unsigned)&UEP2*8+0;
volatile bit UOWN_0O @ (unsigned)&BD0OST*8+7;
volatile bit DATA_0O @ (unsigned)&BD0OST*8+6;
volatile bit PID3_0O @ (unsigned)&BD0OST*8+5;
volatile bit PID2_0O @ (unsigned)&BD0OST*8+4;
volatile bit PID1_0O @ (unsigned)&BD0OST*8+3;
volatile bit PID0_0O @ (unsigned)&BD0OST*8+2;
volatile bit UOWN_0I @ (unsigned)&BD0IST*8+7;
volatile bit DATA_0I @ (unsigned)&BD0IST*8+6;
volatile bit PID3_0I @ (unsigned)&BD0IST*8+5;
volatile bit PID2_0I @ (unsigned)&BD0IST*8+4;
volatile bit PID1_0I @ (unsigned)&BD0IST*8+3;
volatile bit PID0_0I @ (unsigned)&BD0IST*8+2;
volatile bit UOWN_1O @ (unsigned)&BD1OST*8+7;
volatile bit DATA_1O @ (unsigned)&BD1OST*8+6;
volatile bit PID3_1O @ (unsigned)&BD1OST*8+5;
volatile bit PID2_1O @ (unsigned)&BD1OST*8+4;
volatile bit PID1_1O @ (unsigned)&BD1OST*8+3;
volatile bit PID0_1O @ (unsigned)&BD1OST*8+2;
volatile bit UOWN_1I @ (unsigned)&BD1IST*8+7;
volatile bit DATA_1I @ (unsigned)&BD1IST*8+6;
volatile bit PID3_1I @ (unsigned)&BD1IST*8+5;
volatile bit PID2_1I @ (unsigned)&BD1IST*8+4;
volatile bit PID1_1I @ (unsigned)&BD1IST*8+3;
volatile bit PID0_1I @ (unsigned)&BD1IST*8+2;
volatile bit UOWN_2O @ (unsigned)&BD2OST*8+7;
volatile bit DATA_2O @ (unsigned)&BD2OST*8+6;
volatile bit PID3_2O @ (unsigned)&BD2OST*8+5;
volatile bit PID2_2O @ (unsigned)&BD2OST*8+4;
volatile bit PID1_2O @ (unsigned)&BD2OST*8+3;
volatile bit PID0_2O @ (unsigned)&BD2OST*8+2;
volatile bit UOWN_2I @ (unsigned)&BD2IST*8+7;
volatile bit DATA_2I @ (unsigned)&BD2IST*8+6;
volatile bit PID3_2I @ (unsigned)&BD2IST*8+5;
volatile bit PID2_2I @ (unsigned)&BD2IST*8+4;
volatile bit PID1_2I @ (unsigned)&BD2IST*8+3;
volatile bit PID0_2I @ (unsigned)&BD2IST*8+2;
#endif
/* A full configuration word includes one of each group ORed together */
#define CONFIG_ADDR 0x2007
#if !defined(_16C745) || !defined(_16C765)
/*brown out reset*/
#define BOREN 0xFFFF // enable brown out reset
#define BORDIS 0xF3BF // disable brown out reset
/*Brown out voltage level*/
#define BORV25 0xFFFF // Brown out reset voltage is 2.5 volts
#define BORV27 0xFBFF // Brown out reset voltage is 2.7 volts
#define BORV42 0xF7FF // Brown out reset voltage is 4.2 volts
#define BORV45 0xF3FF // Brown out reset voltage is 4.5 volts
// alternative definitions
#define VBOR_25 0xFFFF // use BORV25
#define VBOR_27 0xFBFF // use BORV27
#define VBOR_42 0xF7FF // use BORV42
#define VBOR_45 0xF3FF // use BORV45
#define VBOR_OFF 0xF3BF // use BORDIS
#endif
/* Programming Notes
BODEN BORV
1 (BODEN_ON) 11 2.5 volts (VBOR_25)
1 (BODEN_ON) 10 2.7 volts (VBOR_27)
1 (BODEN_ON) 01 4.2 volts (VBOR_42)
1 (BODEN_ON) 00 4.5 volts (VBOR_45)
0 (BODEN_OFF) 00 Brown out off (VBOR_OFF)
0 (BODEN_OFF) 01 Illegal (VBOR_42)
0 (BODEN_OFF) 10 Illegal (VBOR_27)
0 (BODEN_OFF) 11 Illegal (VBOR_25)
*/
/*code protection*/
#if defined(_16C717)
#define PROTECT 0x0CFF /* enable code protection */
#elif defined (_16C770) || defined (_16C771)
#define PROTECT 0x004F /* enable code protection */
#elif defined(_16C773) || defined (_16C774)
#define PROTECT 0x0CCF /* enable code protection */
#define PROTECT75 0x1DDF /* code protection 75% */
#define PROTECT50 0x2EEF /* code protection 50% */
#elif defined(_16C745) || defined (_16C765)
#define PROTECT 0x00CF /* enable code protection */
#define PROTECT75 0x15DF /* code protection 75% */
#define PROTECT50 0x2AEF /* code protection 50% */
#endif
#define UNPROTECT 0x3FFF /* do not protect the code */
/* watchdog and power up timer */
#define WDTEN 0x3FFF /* enable watchdog timer */
#define PWRTDIS 0x3FFF /* disable power up timer */
#if defined(_16C717)
#define WDTDIS 0x3FF7 /* disable watchdog timer */
#define PWRTEN 0x3FEF /* enable power up timer */
/* MCLR Pin function */
#define MCLREN 0x3FFF /* master clear reset enable */
#define MCLRDIS 0x3FDF /* master clear reset disable */
#else
#define WDTDIS 0x3FFB /* disable watchdog timer */
#define PWRTEN 0x3FF7 /* enable power up timer */
#endif
/*osc configurations*/
#if defined(_16C717)
#define LP 0x3FF8 /* low power crystal */
#define XT 0x3FF9 /* crystal/resonator */
#define HS 0x3FFA /* high speed crystal */
#define EC 0x3FFB /* RA7=external clkin/RA6=IO */
#define INTRCIO 0x3FFC /* internal RC oscillator/RA6=IO/RA7=IO */
#define INTRCCLKO 0x3FFD /* internal RC oscillator/RA6=CLKOUT/RA7=IO */
#define ERIO 0x3FFE /* external resistor on RA7/RA6=IO */
#define ERCLKO 0x3FFF /* external resistor on RA7/RA6=CLKOUT */
#endif
#if defined(_16C773) || defined (_16C774) || defined (_16C770) || defined (_16C771)
#define RC 0x3FFF /* resistor/capacitor */
#define HS 0x3FFE /* high speed crystal/resonator */
#define XT 0x3FFD /* crystal/resonator */
#define LP 0x3FFC /* low power crystal/resonator */
#endif
#if defined(_16C745) || defined (_16C765)
#define EC 0x3FFD /* external clock */
#define HS 0x3FFC /* high speed crystal oscillator */
#define E4 0x3FFF /* EC with 4x PLL enabled */
#define H4 0x3FFE /* HS with 4x PLL enabled */
#endif
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