pic16f7x7.h

picc

               bit	ADCS0		@ ((unsigned)&ADCON0*8)+6;
               bit	ADCS1		@ ((unsigned)&ADCON0*8)+7;

/* Definitions for OPTION register */
               bit	PS0		@ ((unsigned)&OPTION*8)+0;
               bit	PS1		@ ((unsigned)&OPTION*8)+1;
               bit	PS2		@ ((unsigned)&OPTION*8)+2;
               bit	PSA		@ ((unsigned)&OPTION*8)+3;
               bit	T0SE		@ ((unsigned)&OPTION*8)+4;
               bit	T0CS		@ ((unsigned)&OPTION*8)+5;
               bit	INTEDG		@ ((unsigned)&OPTION*8)+6;
               bit	RBPU		@ ((unsigned)&OPTION*8)+7;

/* Definitions for TRISA register */
volatile       bit	TRISA0		@ ((unsigned)&TRISA*8)+0;
volatile       bit	TRISA1		@ ((unsigned)&TRISA*8)+1;
volatile       bit	TRISA2		@ ((unsigned)&TRISA*8)+2;
volatile       bit	TRISA3		@ ((unsigned)&TRISA*8)+3;
volatile       bit	TRISA4		@ ((unsigned)&TRISA*8)+4;
volatile       bit	TRISA5		@ ((unsigned)&TRISA*8)+5;
volatile       bit	TRISA6		@ ((unsigned)&TRISA*8)+6;
volatile       bit	TRISA7		@ ((unsigned)&TRISA*8)+7;

/* Definitions for TRISB register */
volatile       bit	TRISB0		@ ((unsigned)&TRISB*8)+0;
volatile       bit	TRISB1		@ ((unsigned)&TRISB*8)+1;
volatile       bit	TRISB2		@ ((unsigned)&TRISB*8)+2;
volatile       bit	TRISB3		@ ((unsigned)&TRISB*8)+3;
volatile       bit	TRISB4		@ ((unsigned)&TRISB*8)+4;
volatile       bit	TRISB5		@ ((unsigned)&TRISB*8)+5;
volatile       bit	TRISB6		@ ((unsigned)&TRISB*8)+6;
volatile       bit	TRISB7		@ ((unsigned)&TRISB*8)+7;

/* Definitions for TRISC register */
volatile       bit	TRISC0		@ ((unsigned)&TRISC*8)+0;
volatile       bit	TRISC1		@ ((unsigned)&TRISC*8)+1;
volatile       bit	TRISC2		@ ((unsigned)&TRISC*8)+2;
volatile       bit	TRISC3		@ ((unsigned)&TRISC*8)+3;
volatile       bit	TRISC4		@ ((unsigned)&TRISC*8)+4;
volatile       bit	TRISC5		@ ((unsigned)&TRISC*8)+5;
volatile       bit	TRISC6		@ ((unsigned)&TRISC*8)+6;
volatile       bit	TRISC7		@ ((unsigned)&TRISC*8)+7;

#if defined(_16F747) || defined(_16F777)
/* Definitions for TRISD register */
volatile       bit	TRISD0		@ ((unsigned)&TRISD*8)+0;
volatile       bit	TRISD1		@ ((unsigned)&TRISD*8)+1;
volatile       bit	TRISD2		@ ((unsigned)&TRISD*8)+2;
volatile       bit	TRISD3		@ ((unsigned)&TRISD*8)+3;
volatile       bit	TRISD4		@ ((unsigned)&TRISD*8)+4;
volatile       bit	TRISD5		@ ((unsigned)&TRISD*8)+5;
volatile       bit	TRISD6		@ ((unsigned)&TRISD*8)+6;
volatile       bit	TRISD7		@ ((unsigned)&TRISD*8)+7;

/* Definitions for TRISE register */
volatile       bit	TRISE0		@ ((unsigned)&TRISE*8)+0;
volatile       bit	TRISE1		@ ((unsigned)&TRISE*8)+1;
volatile       bit	TRISE2		@ ((unsigned)&TRISE*8)+2;
               bit	PSPMODE		@ ((unsigned)&TRISE*8)+4;
volatile       bit	IBOV		@ ((unsigned)&TRISE*8)+5;
volatile       bit	OBF		@ ((unsigned)&TRISE*8)+6;
volatile       bit	IBF		@ ((unsigned)&TRISE*8)+7;
#endif

/* Definitions for PIE1 register */
               bit	TMR1IE		@ ((unsigned)&PIE1*8)+0;
               bit	TMR2IE		@ ((unsigned)&PIE1*8)+1;
               bit	CCP1IE		@ ((unsigned)&PIE1*8)+2;
               bit	SSPIE		@ ((unsigned)&PIE1*8)+3;
               bit	TXIE		@ ((unsigned)&PIE1*8)+4;
               bit	RCIE		@ ((unsigned)&PIE1*8)+5;
               bit	ADIE		@ ((unsigned)&PIE1*8)+6;
#if defined(_16F747) || defined(_16F777)
               bit	PSPIE		@ ((unsigned)&PIE1*8)+7;
#endif

/* Definitions for PIE2 register */
               bit	CCP2IE		@ ((unsigned)&PIE2*8)+0;
               bit	CCP3IE		@ ((unsigned)&PIE2*8)+1;
               bit	BCLIE		@ ((unsigned)&PIE2*8)+3;
               bit	LVDIE		@ ((unsigned)&PIE2*8)+5;
               bit	CMIE		@ ((unsigned)&PIE2*8)+6;
               bit	OSFIE		@ ((unsigned)&PIE2*8)+7;

/* Definitions for PCON register */
volatile       bit	BOR		@ ((unsigned)&PCON*8)+0;
volatile       bit	POR		@ ((unsigned)&PCON*8)+1;
               bit	SBOREN		@ ((unsigned)&PCON*8)+2;

/* Definitions for OSCCON register */
               bit	SCS0		@ ((unsigned)&OSCCON*8)+0;
               bit	SCS1		@ ((unsigned)&OSCCON*8)+1;
volatile       bit	IOFS		@ ((unsigned)&OSCCON*8)+2;
volatile       bit	OSTS		@ ((unsigned)&OSCCON*8)+3;
               bit	IRCF0		@ ((unsigned)&OSCCON*8)+4;
               bit	IRCF1		@ ((unsigned)&OSCCON*8)+5;
               bit	IRCF2		@ ((unsigned)&OSCCON*8)+6;

/* Definitions for OSCTUNE register */
               bit	TUN0		@ ((unsigned)&OSCTUNE*8)+0;
               bit	TUN1		@ ((unsigned)&OSCTUNE*8)+1;
               bit	TUN2		@ ((unsigned)&OSCTUNE*8)+2;
               bit	TUN3		@ ((unsigned)&OSCTUNE*8)+3;
               bit	TUN4		@ ((unsigned)&OSCTUNE*8)+4;
               bit	TUN5		@ ((unsigned)&OSCTUNE*8)+5;

/* Definitions for SSPCON2 register */
               bit	SEN		@ ((unsigned)&SSPCON2*8)+0;
volatile       bit	RSEN		@ ((unsigned)&SSPCON2*8)+1;
volatile       bit	PEN		@ ((unsigned)&SSPCON2*8)+2;
volatile       bit	RCEN		@ ((unsigned)&SSPCON2*8)+3;
volatile       bit	ACKEN		@ ((unsigned)&SSPCON2*8)+4;
volatile       bit	ACKDT		@ ((unsigned)&SSPCON2*8)+5;
volatile       bit	ACKSTAT		@ ((unsigned)&SSPCON2*8)+6;
               bit	GCEN		@ ((unsigned)&SSPCON2*8)+7;

/* Definitions for SSPSTAT register */
volatile       bit	BF		@ ((unsigned)&SSPSTAT*8)+0;
volatile       bit	UA		@ ((unsigned)&SSPSTAT*8)+1;
volatile       bit	RW		@ ((unsigned)&SSPSTAT*8)+2;
volatile       bit	START		@ ((unsigned)&SSPSTAT*8)+3;
volatile       bit	STOP		@ ((unsigned)&SSPSTAT*8)+4;
volatile       bit	DA		@ ((unsigned)&SSPSTAT*8)+5;
               bit	CKE		@ ((unsigned)&SSPSTAT*8)+6;
               bit	SMP		@ ((unsigned)&SSPSTAT*8)+7;

/* Definitions for CCP3CON register */
               bit	CCP3M0		@ ((unsigned)&CCP3CON*8)+0;
               bit	CCP3M1		@ ((unsigned)&CCP3CON*8)+1;
               bit	CCP3M2		@ ((unsigned)&CCP3CON*8)+2;
               bit	CCP3M3		@ ((unsigned)&CCP3CON*8)+3;
volatile       bit	CCP3Y		@ ((unsigned)&CCP3CON*8)+4;
volatile       bit	CCP3X		@ ((unsigned)&CCP3CON*8)+5;

/* Definitions for TXSTA register */
volatile       bit	TX9D		@ ((unsigned)&TXSTA*8)+0;
volatile       bit	TRMT		@ ((unsigned)&TXSTA*8)+1;
               bit	BRGH		@ ((unsigned)&TXSTA*8)+2;
               bit	SYNC		@ ((unsigned)&TXSTA*8)+4;
               bit	TXEN		@ ((unsigned)&TXSTA*8)+5;
               bit	TX9		@ ((unsigned)&TXSTA*8)+6;
               bit	CSRC		@ ((unsigned)&TXSTA*8)+7;

/* Definitions for ADCON2 register */
               bit	ACQT0		@ ((unsigned)&ADCON2*8)+2;
               bit	ACQT1		@ ((unsigned)&ADCON2*8)+3;
               bit	ACQT2		@ ((unsigned)&ADCON2*8)+4;

/* Definitions for CMCON register */
               bit	CM0		@ ((unsigned)&CMCON*8)+0;
               bit	CM1		@ ((unsigned)&CMCON*8)+1;
               bit	CM2		@ ((unsigned)&CMCON*8)+2;
               bit	CIS		@ ((unsigned)&CMCON*8)+3;
               bit	C1INV		@ ((unsigned)&CMCON*8)+4;
               bit	C2INV		@ ((unsigned)&CMCON*8)+5;
volatile       bit	C1OUT		@ ((unsigned)&CMCON*8)+6;
volatile       bit	C2OUT		@ ((unsigned)&CMCON*8)+7;

/* Definitions for CVRCON register */
               bit	CVR0		@ ((unsigned)&CVRCON*8)+0;
               bit	CVR1		@ ((unsigned)&CVRCON*8)+1;
               bit	CVR2		@ ((unsigned)&CVRCON*8)+2;
               bit	CVR3		@ ((unsigned)&CVRCON*8)+3;
               bit	CVRR		@ ((unsigned)&CVRCON*8)+5;
               bit	CVROE		@ ((unsigned)&CVRCON*8)+6;
               bit	CVREN		@ ((unsigned)&CVRCON*8)+7;

/* Definitions for ADCON1 register */
               bit	PCFG0		@ ((unsigned)&ADCON1*8)+0;
               bit	PCFG1		@ ((unsigned)&ADCON1*8)+1;
               bit	PCFG2		@ ((unsigned)&ADCON1*8)+2;
               bit	PCFG3		@ ((unsigned)&ADCON1*8)+3;
               bit	VCFG0		@ ((unsigned)&ADCON1*8)+4;
               bit	VCFG1		@ ((unsigned)&ADCON1*8)+5;
               bit	ADCS2		@ ((unsigned)&ADCON1*8)+6;
               bit	ADFM		@ ((unsigned)&ADCON1*8)+7;

/* Definitions for WDTCON register */
               bit	SWDTEN		@ ((unsigned)&WDTCON*8)+0;
               bit	WDTPS0		@ ((unsigned)&WDTCON*8)+1;
               bit	WDTPS1		@ ((unsigned)&WDTCON*8)+2;
               bit	WDTPS2		@ ((unsigned)&WDTCON*8)+3;
               bit	WDTPS3		@ ((unsigned)&WDTCON*8)+4;

/* Definitions for LVDCON register */
               bit	LVDL0		@ ((unsigned)&LVDCON*8)+0;
               bit	LVDL1		@ ((unsigned)&LVDCON*8)+1;
               bit	LVDL2		@ ((unsigned)&LVDCON*8)+2;
               bit	LVDL3		@ ((unsigned)&LVDCON*8)+3;
               bit	LVDEN		@ ((unsigned)&LVDCON*8)+4;
volatile       bit	IRVST		@ ((unsigned)&LVDCON*8)+5;

/* Definitions for EECON1 register */
volatile       bit	RD		@ ((unsigned)&EECON1*8)+0;

/* define to select flash access routines in pic.h */
#define FLASH_TYPE_R
	

// Configuration Mask Definitions
#define CONFIG_ADDR	0x2007
// Protection of flash memory 
#define PROTECT		0x1FFF
#define UNPROTECT	0x3FFF
// CCP multiplex pin selection 
#define CCPRC1		0x3FFF
#define CCPRB3		0x2FFF
// In-Circuit Debugger Mode 
#define DEBUGEN		0x37FF
#define DEBUGDIS	0x3FFF
// Brown-Out reset enable (combines with BORSEN) 
#define BORV20		0x3FFF
#define BORV27		0x3F7F
#define BORV42		0x3EFF
#define BORV45		0x3E7F
#define BORON		0x3FFF
#define BORDIS		0x3FBF
// Master clear reset pin function
#define MCLREN		0x3FFF
#define MCLRDIS		0x3FDF
// Power up timer enable 
#define PWRTEN		0x3FF7
#define PWRTDIS		0x3FFF
// Watchdog timer enable 
#define WDTEN		0x3FFF
#define WDTDIS		0x3FFB
// Oscillator configurations 
#define RCCLK		0x3FFF
#define RCIO		0x3FFE
#define INTCLK		0x3FFD
#define INTIO		0x3FFC
#define EC		0x3FEF
#define HS		0x3FEE
#define XT		0x3FED
#define LP		0x3FEC
#define CONFIG_ADDR2	0x2008
// Brown-Out reset enable (combines with BOREN) 
#define BORSOFT		0x3FFF
#define BORDISSLEEP	0x3FBF
// Internal External switch over 
#define IESOEN		0x3FFF
#define IESODIS		0x3FFD
// Fail-safe clock monitor 
#define FCMEN		0x3FFF
#define FCMDIS		0x3FFE

#endif