as16f1526.h

picc

; HI-TECH Software PICC Assembler header file.
; Definitions based on C header file: pic16f1526.h.

; NOTE: PICC assembler option -P is required to preprocess assembler sources. 

; Special Function Register definitions
INDF0		equ	0000h
INDF1		equ	0001h
PCL		equ	0002h
STATUS		equ	0003h
FSR0L		equ	0004h
FSR0H		equ	0005h
FSR1L		equ	0006h
FSR1H		equ	0007h
BSR		equ	0008h
WREG		equ	0009h
PCLATH		equ	000Ah
INTCON		equ	000Bh
PORTA		equ	000Ch
PORTB		equ	000Dh
PORTC		equ	000Eh
PORTD		equ	000Fh
PORTE		equ	0010h
PIR1		equ	0011h
PIR2		equ	0012h
PIR3		equ	0013h
PIR4		equ	0014h
TMR0		equ	0015h
TMR1L		equ	0016h
TMR1H		equ	0017h
T1CON		equ	0018h
T1GCON		equ	0019h
TMR2		equ	001Ah
PR2		equ	001Bh
T2CON		equ	001Ch
TRIS_REGA		equ	008Ch
TRIS_REGB		equ	008Dh
TRIS_REGC		equ	008Eh
TRIS_REGD		equ	008Fh
TRIS_REGE		equ	0090h
PIE1		equ	0091h
PIE2		equ	0092h
PIE3		equ	0093h
PIE4		equ	0094h
OPTION_REG_REG	equ	0095h
PCON		equ	0096h
WDTCON		equ	0097h
OSCCON		equ	0099h
OSCSTAT		equ	009Ah
ADRESL		equ	009Bh
ADRESH		equ	009Ch
ADCON0		equ	009Dh
ADCON1		equ	009Eh
LATA		equ	010Ch
LATB		equ	010Dh
LATC		equ	010Eh
LATD		equ	010Fh
LATE		equ	0110h
BORCON		equ	0116h
FVRCON		equ	0117h
APFCON		equ	011Dh
ANSELA		equ	018Ch
ANSELB		equ	018Dh
ANSELD		equ	018Fh
ANSELE		equ	0190h
PMADRL		equ	0191h
PMADRH		equ	0192h
PMDATL		equ	0193h
PMDATH		equ	0194h
PMCON1		equ	0195h
PMCON2		equ	0196h
VREGCON		equ	0197h
RC1REG		equ	0199h
RCREG		equ	0199h
RCREG1		equ	0199h
TX1REG		equ	019Ah
TXREG		equ	019Ah
TXREG1		equ	019Ah
SP1BRGL		equ	019Bh
SPBRG		equ	019Bh
SPBRGL		equ	019Bh
SPBRGL1		equ	019Bh
SP1BRGH		equ	019Ch
SPBRGH		equ	019Ch
SPBRGH1		equ	019Ch
RC1STA		equ	019Dh
RCSTA		equ	019Dh
RCSTA1		equ	019Dh
TX1STA		equ	019Eh
TXSTA		equ	019Eh
TXSTA1		equ	019Eh
BAUD1CON	equ	019Fh
BAUDCON		equ	019Fh
BAUDCON1	equ	019Fh
WPUB		equ	020Dh
WPUD		equ	020Fh
WPUE		equ	0210h
SSP1BUF		equ	0211h
SSPBUF		equ	0211h
SSP1ADD		equ	0212h
SSPADD		equ	0212h
SSP1MSK		equ	0213h
SSPMSK		equ	0213h
SSP1STAT	equ	0214h
SSPSTAT		equ	0214h
SSP1CON1	equ	0215h
SSPCON		equ	0215h
SSPCON1		equ	0215h
SSP1CON2	equ	0216h
SSPCON2		equ	0216h
SSP1CON3	equ	0217h
SSPCON3		equ	0217h
SSP2BUF		equ	0219h
SSP2ADD		equ	021Ah
SSP2MSK		equ	021Bh
SSP2STAT	equ	021Ch
SSP2CON1	equ	021Dh
SSP2CON2	equ	021Eh
SSP2CON3	equ	021Fh
PORTF		equ	028Ch
PORTG		equ	028Dh
CCPR1L		equ	0291h
CCPR1H		equ	0292h
CCP1CON		equ	0293h
CCPR2L		equ	0298h
CCPR2H		equ	0299h
CCP2CON		equ	029Ah
CCPTMRS0	equ	029Dh
CCPTMRS1	equ	029Eh
CCPTMRS2	equ	029Fh
TRIS_REGF		equ	030Ch
TRIS_REGG		equ	030Dh
CCPR3L		equ	0311h
CCPR3H		equ	0312h
CCP3CON		equ	0313h
CCPR4L		equ	0318h
CCPR4H		equ	0319h
CCP4CON		equ	031Ah
CCPR5L		equ	031Ch
CCPR5H		equ	031Dh
CCP5CON		equ	031Eh
LATF		equ	038Ch
LATG		equ	038Dh
IOCBP		equ	0394h
IOCBN		equ	0395h
IOCBF		equ	0396h
ANSELF		equ	040Ch
ANSELG		equ	040Dh
TMR3L		equ	0411h
TMR3H		equ	0412h
T3CON		equ	0413h
T3GCON		equ	0414h
TMR4		equ	0415h
PR4		equ	0416h
T4CON		equ	0417h
TMR5L		equ	0418h
TMR5H		equ	0419h
T5CON		equ	041Ah
T5GCON		equ	041Bh
TMR6		equ	041Ch
PR6		equ	041Dh
T6CON		equ	041Eh
WPUG		equ	048Dh
RC2REG		equ	0491h
RCREG2		equ	0491h
TX2REG		equ	0492h
TXREG2		equ	0492h
SP2BRGL		equ	0493h
SPBRGL2		equ	0493h
SP2BRGH		equ	0494h
SPBRGH2		equ	0494h
RC2STA		equ	0495h
RCSTA2		equ	0495h
TX2STA		equ	0496h
TXSTA2		equ	0496h
BAUD2CON	equ	0497h
BAUDCON2	equ	0497h
TMR8		equ	0595h
PR8		equ	0596h
T8CON		equ	0597h
TMR10		equ	059Ch
PR10		equ	059Dh
T10CON		equ	059Eh
CCPR6L		equ	0611h
CCPR6H		equ	0612h
CCP6CON		equ	0613h
CCPR7L		equ	0614h
CCPR7H		equ	0615h
CCP7CON		equ	0616h
CCPR8L		equ	0617h
CCPR8H		equ	0618h
CCP8CON		equ	0619h
CCPR9L		equ	061Ah
CCPR9H		equ	061Bh
CCP9CON		equ	061Ch
CCPR10L		equ	061Dh
CCPR10H		equ	061Eh
CCP10CON	equ	061Fh
STATUS_SHAD	equ	0FE4h
WREG_SHAD	equ	0FE5h
BSR_SHAD	equ	0FE6h
PCLATH_SHAD	equ	0FE7h
FSR0L_SHAD	equ	0FE8h
FSR0H_SHAD	equ	0FE9h
FSR1L_SHAD	equ	0FEAh
FSR1H_SHAD	equ	0FEBh
STKPTR		equ	0FEDh
TOSL		equ	0FEEh
TOSH		equ	0FEFh

; Bit variables associates within SFRs
#define CARRY	STATUS,0
#define DC	STATUS,1
#define ZERO	STATUS,2
#define nPD	STATUS,3
#define nTO	STATUS,4
#define BSR0	BSR,0
#define BSR1	BSR,1
#define BSR2	BSR,2
#define BSR3	BSR,3
#define BSR4	BSR,4
#define IOCIF	INTCON,0
#define INTF	INTCON,1
#define TMR0IF	INTCON,2
#define IOCIE	INTCON,3
#define INTE	INTCON,4
#define TMR0IE	INTCON,5
#define PEIE	INTCON,6
#define GIE	INTCON,7
#define T0IF	INTCON,2
#define T0IE	INTCON,5
#define RA0	PORTA,0
#define RA1	PORTA,1
#define RA2	PORTA,2
#define RA3	PORTA,3
#define RA4	PORTA,4
#define RA5	PORTA,5
#define RA6	PORTA,6
#define RA7	PORTA,7
#define RB0	PORTB,0
#define RB1	PORTB,1
#define RB2	PORTB,2
#define RB3	PORTB,3
#define RB4	PORTB,4
#define RB5	PORTB,5
#define RB6	PORTB,6
#define RB7	PORTB,7
#define RC0	PORTC,0
#define RC1	PORTC,1
#define RC2	PORTC,2
#define RC3	PORTC,3
#define RC4	PORTC,4
#define RC5	PORTC,5
#define RC6	PORTC,6
#define RC7	PORTC,7
#define RD0	PORTD,0
#define RD1	PORTD,1
#define RD2	PORTD,2
#define RD3	PORTD,3
#define RD4	PORTD,4
#define RD5	PORTD,5
#define RD6	PORTD,6
#define RD7	PORTD,7
#define RE0	PORTE,0
#define RE1	PORTE,1
#define RE2	PORTE,2
#define RE3	PORTE,3
#define RE4	PORTE,4
#define RE5	PORTE,5
#define RE6	PORTE,6
#define RE7	PORTE,7
#define TMR1IF	PIR1,0
#define TMR2IF	PIR1,1
#define CCP1IF	PIR1,2
#define SSP1IF	PIR1,3
#define TX1IF	PIR1,4
#define RC1IF	PIR1,5
#define ADIF	PIR1,6
#define TMR1GIF	PIR1,7
#define SSPIF	PIR1,3
#define TXIF	PIR1,4
#define RCIF	PIR1,5
#define CCP2IF	PIR2,0
#define TMR8IF	PIR2,1
#define TMR10IF	PIR2,2
#define BCL1IF	PIR2,3
#define TMR3GIF	PIR2,5
#define TMR5GIF	PIR2,6
#define OSFIF	PIR2,7
#define BCLIF	PIR2,3
#define TMR3IF	PIR3,0
#define TMR4IF	PIR3,1
#define TMR5IF	PIR3,2
#define TMR6IF	PIR3,3
#define CCP3IF	PIR3,4
#define CCP4IF	PIR3,5
#define CCP5IF	PIR3,6
#define CCP6IF	PIR3,7
#define SSP2IF	PIR4,0
#define BCL2IF	PIR4,1
#define CCP7IF	PIR4,2
#define CCP8IF	PIR4,3
#define TX2IF	PIR4,4
#define RC2IF	PIR4,5
#define CCP9IF	PIR4,6
#define CCP10IF	PIR4,7
#define TMR1ON	T1CON,0
#define nT1SYNC	T1CON,2
#define T1OSCEN	T1CON,3
#define T1CKPS0	T1CON,4
#define T1CKPS1	T1CON,5
#define TMR1CS0	T1CON,6
#define TMR1CS1	T1CON,7
#define T1GSS0	T1GCON,0
#define T1GSS1	T1GCON,1
#define T1GVAL	T1GCON,2
#define T1GGO_nDONE	T1GCON,3
#define T1GSPM	T1GCON,4
#define T1GTM	T1GCON,5
#define T1GPOL	T1GCON,6
#define TMR1GE	T1GCON,7
#define T2CKPS0	T2CON,0
#define T2CKPS1	T2CON,1
#define TMR2ON	T2CON,2
#define T2OUTPS0	T2CON,3
#define T2OUTPS1	T2CON,4
#define T2OUTPS2	T2CON,5
#define T2OUTPS3	T2CON,6
#define TRIS_REGA0	TRIS_REGA,0
#define TRIS_REGA1	TRIS_REGA,1
#define TRIS_REGA2	TRIS_REGA,2
#define TRIS_REGA3	TRIS_REGA,3
#define TRIS_REGA4	TRIS_REGA,4
#define TRIS_REGA5	TRIS_REGA,5
#define TRIS_REGA6	TRIS_REGA,6
#define TRIS_REGA7	TRIS_REGA,7
#define TRIS_REGB0	TRIS_REGB,0
#define TRIS_REGB1	TRIS_REGB,1
#define TRIS_REGB2	TRIS_REGB,2
#define TRIS_REGB3	TRIS_REGB,3
#define TRIS_REGB4	TRIS_REGB,4
#define TRIS_REGB5	TRIS_REGB,5
#define TRIS_REGB6	TRIS_REGB,6
#define TRIS_REGB7	TRIS_REGB,7
#define TRIS_REGC0	TRIS_REGC,0
#define TRIS_REGC1	TRIS_REGC,1
#define TRIS_REGC2	TRIS_REGC,2
#define TRIS_REGC3	TRIS_REGC,3
#define TRIS_REGC4	TRIS_REGC,4
#define TRIS_REGC5	TRIS_REGC,5
#define TRIS_REGC6	TRIS_REGC,6
#define TRIS_REGC7	TRIS_REGC,7
#define TRIS_REGD0	TRIS_REGD,0
#define TRIS_REGD1	TRIS_REGD,1
#define TRIS_REGD2	TRIS_REGD,2
#define TRIS_REGD3	TRIS_REGD,3
#define TRIS_REGD4	TRIS_REGD,4
#define TRIS_REGD5	TRIS_REGD,5
#define TRIS_REGD6	TRIS_REGD,6
#define TRIS_REGD7	TRIS_REGD,7
#define TRIS_REGE0	TRIS_REGE,0
#define TRIS_REGE1	TRIS_REGE,1
#define TRIS_REGE2	TRIS_REGE,2
#define TRIS_REGE3	TRIS_REGE,3
#define TRIS_REGE4	TRIS_REGE,4
#define TRIS_REGE5	TRIS_REGE,5
#define TRIS_REGE6	TRIS_REGE,6
#define TRIS_REGE7	TRIS_REGE,7
#define TMR1IE	PIE1,0
#define TMR2IE	PIE1,1
#define CCP1IE	PIE1,2
#define SSP1IE	PIE1,3
#define TX1IE	PIE1,4
#define RC1IE	PIE1,5
#define ADIE	PIE1,6
#define TMR1GIE	PIE1,7
#define SSPIE	PIE1,3
#define TXIE	PIE1,4
#define RCIE	PIE1,5
#define CCP2IE	PIE2,0
#define TMR8IE	PIE2,1
#define TMR10IE	PIE2,2
#define BCL1IE	PIE2,3
#define TMR3GIE	PIE2,5
#define TMR5GIE	PIE2,6