cas16lf1847.h

picc

; HI-TECH Software PICC Assembler header file.
; Definitions based on C header file: pic16lf1847.h.

; NOTE: PICC assembler option -P is required to preprocess assembler sources. 

; Special Function Register definitions
INDF0		equ	0000h
INDF1		equ	0001h
PCL		equ	0002h
STATUS		equ	0003h
FSR0L		equ	0004h
FSR0H		equ	0005h
FSR1L		equ	0006h
FSR1H		equ	0007h
BSR		equ	0008h
WREG		equ	0009h
PCLATH		equ	000Ah
INTCON		equ	000Bh
PORTA		equ	000Ch
PORTB		equ	000Dh
PIR1		equ	0011h
PIR2		equ	0012h
PIR3		equ	0013h
PIR4		equ	0014h
TMR0		equ	0015h
TMR1L		equ	0016h
TMR1H		equ	0017h
T1CON		equ	0018h
T1GCON		equ	0019h
TMR2		equ	001Ah
PR2		equ	001Bh
T2CON		equ	001Ch
CPSCON0		equ	001Eh
CPSCON1		equ	001Fh
TRIS_REGA		equ	008Ch
TRIS_REGB		equ	008Dh
PIE1		equ	0091h
PIE2		equ	0092h
PIE3		equ	0093h
PIE4		equ	0094h
OPTION_REG_REG	equ	0095h
PCON		equ	0096h
WDTCON		equ	0097h
OSCTUNE		equ	0098h
OSCCON		equ	0099h
OSCSTAT		equ	009Ah
ADRESL		equ	009Bh
ADRESH		equ	009Ch
ADCON0		equ	009Dh
ADCON1		equ	009Eh
LATA		equ	010Ch
LATB		equ	010Dh
CM1CON0		equ	0111h
CM1CON1		equ	0112h
CM2CON0		equ	0113h
CM2CON1		equ	0114h
CMOUT		equ	0115h
BORCON		equ	0116h
FVRCON		equ	0117h
DACCON0		equ	0118h
DACCON1		equ	0119h
SRCON0		equ	011Ah
SRCON1		equ	011Bh
APFCON0		equ	011Dh
APFCON1		equ	011Eh
ANSELA		equ	018Ch
ANSELB		equ	018Dh
EEADRL		equ	0191h
EEADRH		equ	0192h
EEDATL		equ	0193h
EEDATA		equ	0193h
EEDATH		equ	0194h
EECON1		equ	0195h
EECON2		equ	0196h
RCREG		equ	0199h
TXREG		equ	019Ah
SPBRGL		equ	019Bh
SPBRG		equ	019Bh
SPBRGH		equ	019Ch
RCSTA		equ	019Dh
TXSTA		equ	019Eh
BAUDCON		equ	019Fh
WPUA		equ	020Ch
WPUB		equ	020Dh
SSP1BUF		equ	0211h
SSPBUF		equ	0211h
SSP1ADD		equ	0212h
SSPADD		equ	0212h
SSP1MSK		equ	0213h
SSPMSK		equ	0213h
SSP1STAT	equ	0214h
SSPSTAT		equ	0214h
SSP1CON1	equ	0215h
SSPCON1		equ	0215h
SSPCON		equ	0215h
SSP1CON2	equ	0216h
SSPCON2		equ	0216h
SSP1CON3	equ	0217h
SSPCON3		equ	0217h
SSP2BUF		equ	0219h
SSP2ADD		equ	021Ah
SSP2MSK		equ	021Bh
SSP2STAT	equ	021Ch
SSP2CON1	equ	021Dh
SSP2CON2	equ	021Eh
SSP2CON3	equ	021Fh
CCPR1L		equ	0291h
CCPR1H		equ	0292h
CCP1CON		equ	0293h
PWM1CON		equ	0294h
CCP1AS		equ	0295h
ECCP1AS		equ	0295h
PSTR1CON	equ	0296h
CCPR2L		equ	0298h
CCPR2H		equ	0299h
CCP2CON		equ	029Ah
PWM2CON		equ	029Bh
CCP2AS		equ	029Ch
ECCP2AS		equ	029Ch
PSTR2CON	equ	029Dh
CCPTMRS		equ	029Eh
CCPTMRS0	equ	029Eh
CCPR3L		equ	0311h
CCPR3H		equ	0312h
CCP3CON		equ	0313h
CCPR4L		equ	0318h
CCPR4H		equ	0319h
CCP4CON		equ	031Ah
IOCBP		equ	0394h
IOCBN		equ	0395h
IOCBF		equ	0396h
CLKRCON		equ	039Ah
MDCON		equ	039Ch
MDSRC		equ	039Dh
MDCARL		equ	039Eh
MDCARH		equ	039Fh
TMR4		equ	0415h
PR4		equ	0416h
T4CON		equ	0417h
TMR6		equ	041Ch
PR6		equ	041Dh
T6CON		equ	041Eh
STATUS_SHAD	equ	0FE4h
WREG_SHAD	equ	0FE5h
BSR_SHAD	equ	0FE6h
PCLATH_SHAD	equ	0FE7h
FSR0L_SHAD	equ	0FE8h
FSR0H_SHAD	equ	0FE9h
FSR1L_SHAD	equ	0FEAh
FSR1H_SHAD	equ	0FEBh
STKPTR		equ	0FEDh
TOSL		equ	0FEEh
TOSH		equ	0FEFh

; Bit variables associates within SFRs
#define CARRY_bit	STATUS,0
#define DC_bit	STATUS,1
#define ZERO_bit	STATUS,2
#define nPD_bit	STATUS,3
#define nTO_bit	STATUS,4
#define BSR0_bit	BSR,0
#define BSR1_bit	BSR,1
#define BSR2_bit	BSR,2
#define BSR3_bit	BSR,3
#define BSR4_bit	BSR,4
#define IOCIF_bit	INTCON,0
#define INTF_bit	INTCON,1
#define TMR0IF_bit	INTCON,2
#define IOCIE_bit	INTCON,3
#define INTE_bit	INTCON,4
#define TMR0IE_bit	INTCON,5
#define PEIE_bit	INTCON,6
#define GIE_bit	INTCON,7
#define T0IF_bit	INTCON,2
#define T0IE_bit	INTCON,5
#define RA0_bit	PORTA,0
#define RA1_bit	PORTA,1
#define RA2_bit	PORTA,2
#define RA3_bit	PORTA,3
#define RA4_bit	PORTA,4
#define RA5_bit	PORTA,5
#define RA6_bit	PORTA,6
#define RA7_bit	PORTA,7
#define RB0_bit	PORTB,0
#define RB1_bit	PORTB,1
#define RB2_bit	PORTB,2
#define RB3_bit	PORTB,3
#define RB4_bit	PORTB,4
#define RB5_bit	PORTB,5
#define RB6_bit	PORTB,6
#define RB7_bit	PORTB,7
#define TMR1IF_bit	PIR1,0
#define TMR2IF_bit	PIR1,1
#define CCP1IF_bit	PIR1,2
#define SSP1IF_bit	PIR1,3
#define TXIF_bit	PIR1,4
#define RCIF_bit	PIR1,5
#define ADIF_bit	PIR1,6
#define TMR1GIF_bit	PIR1,7
#define CCP2IF_bit	PIR2,0
#define BCL1IF_bit	PIR2,3
#define EEIF_bit	PIR2,4
#define C1IF_bit	PIR2,5
#define C2IF_bit	PIR2,6
#define OSFIF_bit	PIR2,7
#define TMR4IF_bit	PIR3,1
#define TMR6IF_bit	PIR3,3
#define CCP3IF_bit	PIR3,4
#define CCP4IF_bit	PIR3,5
#define SSP2IF_bit	PIR4,0
#define BCL2IF_bit	PIR4,1
#define TMR1ON_bit	T1CON,0
#define nT1SYNC_bit	T1CON,2
#define T1OSCEN_bit	T1CON,3
#define T1CKPS0_bit	T1CON,4
#define T1CKPS1_bit	T1CON,5
#define TMR1CS0_bit	T1CON,6
#define TMR1CS1_bit	T1CON,7
#define T1GSS0_bit	T1GCON,0
#define T1GSS1_bit	T1GCON,1
#define T1GVAL_bit	T1GCON,2
#define T1GGO_bit	T1GCON,3
#define T1GSPM_bit	T1GCON,4
#define T1GTM_bit	T1GCON,5
#define T1GPOL_bit	T1GCON,6
#define TMR1GE_bit	T1GCON,7
#define T2CKPS0_bit	T2CON,0
#define T2CKPS1_bit	T2CON,1
#define TMR2ON_bit	T2CON,2
#define T2OUTPS0_bit	T2CON,3
#define T2OUTPS1_bit	T2CON,4
#define T2OUTPS2_bit	T2CON,5
#define T2OUTPS3_bit	T2CON,6
#define T0XCS_bit	CPSCON0,0
#define CPSOUT_bit	CPSCON0,1
#define CPSRNG0_bit	CPSCON0,2
#define CPSRNG1_bit	CPSCON0,3
#define CPSRM_bit	CPSCON0,6
#define CPSON_bit	CPSCON0,7
#define CPSCH0_bit	CPSCON1,0
#define CPSCH1_bit	CPSCON1,1
#define CPSCH2_bit	CPSCON1,2
#define CPSCH3_bit	CPSCON1,3
#define TRIS_REGA0_bit	TRIS_REGA,0
#define TRIS_REGA1_bit	TRIS_REGA,1
#define TRIS_REGA2_bit	TRIS_REGA,2
#define TRIS_REGA3_bit	TRIS_REGA,3
#define TRIS_REGA4_bit	TRIS_REGA,4
#define TRIS_REGA5_bit	TRIS_REGA,5
#define TRIS_REGA6_bit	TRIS_REGA,6
#define TRIS_REGA7_bit	TRIS_REGA,7
#define TRIS_REGB0_bit	TRIS_REGB,0
#define TRIS_REGB1_bit	TRIS_REGB,1
#define TRIS_REGB2_bit	TRIS_REGB,2
#define TRIS_REGB3_bit	TRIS_REGB,3
#define TRIS_REGB4_bit	TRIS_REGB,4
#define TRIS_REGB5_bit	TRIS_REGB,5
#define TRIS_REGB6_bit	TRIS_REGB,6
#define TRIS_REGB7_bit	TRIS_REGB,7
#define TMR1IE_bit	PIE1,0
#define TMR2IE_bit	PIE1,1
#define CCP1IE_bit	PIE1,2
#define SSP1IE_bit	PIE1,3
#define TXIE_bit	PIE1,4
#define RCIE_bit	PIE1,5
#define ADIE_bit	PIE1,6
#define TMR1GIE_bit	PIE1,7
#define CCP2IE_bit	PIE2,0
#define BCL1IE_bit	PIE2,3
#define EEIE_bit	PIE2,4
#define C1IE_bit	PIE2,5
#define C2IE_bit	PIE2,6
#define OSFIE_bit	PIE2,7
#define TMR4IE_bit	PIE3,1
#define TMR6IE_bit	PIE3,3
#define CCP3IE_bit	PIE3,4
#define CCP4IE_bit	PIE3,5
#define SSP2IE_bit	PIE4,0
#define BCL2IE_bit	PIE4,1
#define PS0_bit	OPTION_REG_REG,0
#define PS1_bit	OPTION_REG_REG,1
#define PS2_bit	OPTION_REG_REG,2
#define PSA_bit	OPTION_REG_REG,3
#define TMR0SE_bit	OPTION_REG_REG,4
#define TMR0CS_bit	OPTION_REG_REG,5
#define INTEDG_bit	OPTION_REG_REG,6
#define nWPUEN_bit	OPTION_REG_REG,7
#define T0SE_bit	OPTION_REG_REG,4
#define T0CS_bit	OPTION_REG_REG,5
#define nBOR_bit	PCON,0
#define nPOR_bit	PCON,1
#define nRI_bit	PCON,2
#define nRMCLR_bit	PCON,3
#define STKUNF_bit	PCON,6
#define STKOVF_bit	PCON,7
#define SWDTEN_bit	WDTCON,0
#define WDTPS0_bit	WDTCON,1
#define WDTPS1_bit	WDTCON,2
#define WDTPS2_bit	WDTCON,3
#define WDTPS3_bit	WDTCON,4
#define WDTPS4_bit	WDTCON,5
#define TUN0_bit	OSCTUNE,0
#define TUN1_bit	OSCTUNE,1
#define TUN2_bit	OSCTUNE,2
#define TUN3_bit	OSCTUNE,3
#define TUN4_bit	OSCTUNE,4
#define TUN5_bit	OSCTUNE,5
#define SCS0_bit	OSCCON,0
#define SCS1_bit	OSCCON,1
#define IRCF0_bit	OSCCON,3
#define IRCF1_bit	OSCCON,4
#define IRCF2_bit	OSCCON,5
#define IRCF3_bit	OSCCON,6
#define SPLLEN_bit	OSCCON,7