📄 pic16f72.h
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//
// Register Declarations for Microchip 16F72 Processor
//
//
// This header file was automatically generated by:
//
// inc2h.pl V1.6
//
// Copyright (c) 2002, Kevin L. Pauba, All Rights Reserved
//
// SDCC is licensed under the GNU Public license (GPL) v2. Note that
// this license covers the code to the compiler and other executables,
// but explicitly does not cover any code or objects generated by sdcc.
// We have not yet decided on a license for the run time libraries, but
// it will not put any requirements on code linked against it. See:
//
// http://www.gnu.org/copyleft/gpl/html
//
// See http://sdcc.sourceforge.net/ for the latest information on sdcc.
//
//
#ifndef P16F72_H
#define P16F72_H
//
// Register addresses.
//
#define INDF_ADDR 0x0000
#define TMR0_ADDR 0x0001
#define PCL_ADDR 0x0002
#define STATUS_ADDR 0x0003
#define FSR_ADDR 0x0004
#define PORTA_ADDR 0x0005
#define PORTB_ADDR 0x0006
#define PORTC_ADDR 0x0007
#define PCLATH_ADDR 0x000A
#define INTCON_ADDR 0x000B
#define PIR1_ADDR 0x000C
#define TMR1L_ADDR 0x000E
#define TMR1H_ADDR 0x000F
#define T1CON_ADDR 0x0010
#define TMR2_ADDR 0x0011
#define T2CON_ADDR 0x0012
#define SSPBUF_ADDR 0x0013
#define SSPCON_ADDR 0x0014
#define CCPR1L_ADDR 0x0015
#define CCPR1H_ADDR 0x0016
#define CCP1CON_ADDR 0x0017
#define ADRES_ADDR 0x001E
#define ADCON0_ADDR 0x001F
#define OPTION_REG_ADDR 0x0081
#define TRISA_ADDR 0x0085
#define TRISB_ADDR 0x0086
#define TRISC_ADDR 0x0087
#define PIE1_ADDR 0x008C
#define PCON_ADDR 0x008E
#define PR2_ADDR 0x0092
#define SSPADD_ADDR 0x0093
#define SSPSTAT_ADDR 0x0094
#define ADCON1_ADDR 0x009F
#define PMDATL_ADDR 0x010C
#define PMADRL_ADDR 0x010D
#define PMDATH_ADDR 0x010E
#define PMADRH_ADDR 0x010F
#define PMCON1_ADDR 0x018C
//
// Memory organization.
//
#pragma memmap INDF_ADDR INDF_ADDR SFR 0x000 // INDF
#pragma memmap TMR0_ADDR TMR0_ADDR SFR 0x000 // TMR0
#pragma memmap PCL_ADDR PCL_ADDR SFR 0x000 // PCL
#pragma memmap STATUS_ADDR STATUS_ADDR SFR 0x000 // STATUS
#pragma memmap FSR_ADDR FSR_ADDR SFR 0x000 // FSR
#pragma memmap PORTA_ADDR PORTA_ADDR SFR 0x000 // PORTA
#pragma memmap PORTB_ADDR PORTB_ADDR SFR 0x000 // PORTB
#pragma memmap PORTC_ADDR PORTC_ADDR SFR 0x000 // PORTC
#pragma memmap PCLATH_ADDR PCLATH_ADDR SFR 0x000 // PCLATH
#pragma memmap INTCON_ADDR INTCON_ADDR SFR 0x000 // INTCON
#pragma memmap PIR1_ADDR PIR1_ADDR SFR 0x000 // PIR1
#pragma memmap TMR1L_ADDR TMR1L_ADDR SFR 0x000 // TMR1L
#pragma memmap TMR1H_ADDR TMR1H_ADDR SFR 0x000 // TMR1H
#pragma memmap T1CON_ADDR T1CON_ADDR SFR 0x000 // T1CON
#pragma memmap TMR2_ADDR TMR2_ADDR SFR 0x000 // TMR2
#pragma memmap T2CON_ADDR T2CON_ADDR SFR 0x000 // T2CON
#pragma memmap SSPBUF_ADDR SSPBUF_ADDR SFR 0x000 // SSPBUF
#pragma memmap SSPCON_ADDR SSPCON_ADDR SFR 0x000 // SSPCON
#pragma memmap CCPR1L_ADDR CCPR1L_ADDR SFR 0x000 // CCPR1L
#pragma memmap CCPR1H_ADDR CCPR1H_ADDR SFR 0x000 // CCPR1H
#pragma memmap CCP1CON_ADDR CCP1CON_ADDR SFR 0x000 // CCP1CON
#pragma memmap ADRES_ADDR ADRES_ADDR SFR 0x000 // ADRES
#pragma memmap ADCON0_ADDR ADCON0_ADDR SFR 0x000 // ADCON0
#pragma memmap OPTION_REG_ADDR OPTION_REG_ADDR SFR 0x000 // OPTION_REG
#pragma memmap TRISA_ADDR TRISA_ADDR SFR 0x000 // TRISA
#pragma memmap TRISB_ADDR TRISB_ADDR SFR 0x000 // TRISB
#pragma memmap TRISC_ADDR TRISC_ADDR SFR 0x000 // TRISC
#pragma memmap PIE1_ADDR PIE1_ADDR SFR 0x000 // PIE1
#pragma memmap PCON_ADDR PCON_ADDR SFR 0x000 // PCON
#pragma memmap PR2_ADDR PR2_ADDR SFR 0x000 // PR2
#pragma memmap SSPADD_ADDR SSPADD_ADDR SFR 0x000 // SSPADD
#pragma memmap SSPSTAT_ADDR SSPSTAT_ADDR SFR 0x000 // SSPSTAT
#pragma memmap ADCON1_ADDR ADCON1_ADDR SFR 0x000 // ADCON1
#pragma memmap PMDATL_ADDR PMDATL_ADDR SFR 0x000 // PMDATL
#pragma memmap PMADRL_ADDR PMADRL_ADDR SFR 0x000 // PMADRL
#pragma memmap PMDATH_ADDR PMDATH_ADDR SFR 0x000 // PMDATH
#pragma memmap PMADRH_ADDR PMADRH_ADDR SFR 0x000 // PMADRH
#pragma memmap PMCON1_ADDR PMCON1_ADDR SFR 0x000 // PMCON1
// LIST
// P16F72.INC Standard Header File, Version 1.01 Microchip Technology, Inc.
// NOLIST
// This header file defines configurations, registers, and other useful bits of
// information for the PIC16F72 microcontroller. These names are taken to match
// the data sheets as closely as possible.
// Note that the processor must be selected before this file is
// included. The processor may be selected the following ways:
// 1. Command line switch:
// C:\ MPASM MYFILE.ASM /PIC16F72
// 2. LIST directive in the source file
// LIST P=PIC16F72
// 3. Processor Type entry in the MPASM full-screen interface
//==========================================================================
//
// Revision History
//
//==========================================================================
//Rev: Date: Reason:
//1.00 03/22/02 Initial Release
//==========================================================================
//
// Verify Processor
//
//==========================================================================
// IFNDEF __16F72
// MESSG "Processor-header file mismatch. Verify selected processor."
// ENDIF
//==========================================================================
//
// Register Definitions
//
//==========================================================================
#define W 0x0000
#define F 0x0001
//----- Register Files------------------------------------------------------
extern __data __at (INDF_ADDR) volatile char INDF;
extern __sfr __at (TMR0_ADDR) TMR0;
extern __data __at (PCL_ADDR) volatile char PCL;
extern __sfr __at (STATUS_ADDR) STATUS;
extern __sfr __at (FSR_ADDR) FSR;
extern __sfr __at (PORTA_ADDR) PORTA;
extern __sfr __at (PORTB_ADDR) PORTB;
extern __sfr __at (PORTC_ADDR) PORTC;
extern __sfr __at (PCLATH_ADDR) PCLATH;
extern __sfr __at (INTCON_ADDR) INTCON;
extern __sfr __at (PIR1_ADDR) PIR1;
extern __sfr __at (TMR1L_ADDR) TMR1L;
extern __sfr __at (TMR1H_ADDR) TMR1H;
extern __sfr __at (T1CON_ADDR) T1CON;
extern __sfr __at (TMR2_ADDR) TMR2;
extern __sfr __at (T2CON_ADDR) T2CON;
extern __sfr __at (SSPBUF_ADDR) SSPBUF;
extern __sfr __at (SSPCON_ADDR) SSPCON;
extern __sfr __at (CCPR1L_ADDR) CCPR1L;
extern __sfr __at (CCPR1H_ADDR) CCPR1H;
extern __sfr __at (CCP1CON_ADDR) CCP1CON;
extern __sfr __at (ADRES_ADDR) ADRES;
extern __sfr __at (ADCON0_ADDR) ADCON0;
extern __sfr __at (OPTION_REG_ADDR) OPTION_REG;
extern __sfr __at (TRISA_ADDR) TRISA;
extern __sfr __at (TRISB_ADDR) TRISB;
extern __sfr __at (TRISC_ADDR) TRISC;
extern __sfr __at (PIE1_ADDR) PIE1;
extern __sfr __at (PCON_ADDR) PCON;
extern __sfr __at (PR2_ADDR) PR2;
extern __sfr __at (SSPADD_ADDR) SSPADD;
extern __sfr __at (SSPSTAT_ADDR) SSPSTAT;
extern __sfr __at (ADCON1_ADDR) ADCON1;
extern __sfr __at (PMDATL_ADDR) PMDATL;
extern __sfr __at (PMADRL_ADDR) PMADRL;
extern __sfr __at (PMDATH_ADDR) PMDATH;
extern __sfr __at (PMADRH_ADDR) PMADRH;
extern __sfr __at (PMCON1_ADDR) PMCON1;
//----- STATUS Bits --------------------------------------------------------
//----- INTCON Bits --------------------------------------------------------
//----- PIR1 Bits ----------------------------------------------------------
//----- T1CON Bits ---------------------------------------------------------
//----- T2CON Bits ---------------------------------------------------------
//----- SSPCON Bits --------------------------------------------------------
//----- CCP1CON Bits -------------------------------------------------------
//----- ADCON0 Bits --------------------------------------------------------
//----- OPTION Bits --------------------------------------------------------
//----- PIE1 Bits ----------------------------------------------------------
//----- PCON Bits ----------------------------------------------------------
//----- SSPSTAT Bits -------------------------------------------------------
//----- ADCON1 Bits --------------------------------------------------------
//----- PMCON1 Bits --------------------------------------------------------
//==========================================================================
//
// RAM Definition
//
//==========================================================================
// __MAXRAM H'1FF'
// __BADRAM H'08'-H'09', H'0D', H'18'-H'1D'
// __BADRAM H'88'-H'89', H'8D', H'8F'-H'91', H'95'-H'9E'
// __BADRAM H'105', H'107'-H'109', H'110'-H'11F'
// __BADRAM H'185', H'187'-H'189', H'18D'-H'19F'
//==========================================================================
//
// Configuration Bits
//
//==========================================================================
#define _BOREN_ON 0x3FFF
#define _BODEN_ON 0x3FFF // Backward compatibility only
#define _BOREN_OFF 0x3FBF
#define _BODEN_OFF 0x3FBF // Backward compatibility only
#define _CP_ALL 0x3FEF
#define _CP_OFF 0x3FFF
#define _PWRTEN_OFF 0x3FFF
#define _PWRTE_OFF 0x3FFF // Backward compatibility only
#define _PWRTEN_ON 0x3FF7
#define _PWRTE_ON 0x3FF7 // Backward compatibility only
#define _WDTEN_ON 0x3FFF
#define _WDTEN_OFF 0x3FFB
#define _WDT_ON 0x3FFF // Backward compatibility only
#define _WDT_OFF 0x3FFB // Backward compatibility only
#define _LP_OSC 0x3FFC
#define _XT_OSC 0x3FFD
#define _HS_OSC 0x3FFE
#define _RC_OSC 0x3FFF
// LIST
// ----- ADCON0 bits --------------------
typedef union {
struct {
unsigned char ADON:1;
unsigned char :1;
unsigned char GO:1;
unsigned char CHS0:1;
unsigned char CHS1:1;
unsigned char CHS2:1;
unsigned char ADCS0:1;
unsigned char ADCS1:1;
};
struct {
unsigned char :1;
unsigned char :1;
unsigned char NOT_DONE:1;
unsigned char :1;
unsigned char :1;
unsigned char :1;
unsigned char :1;
unsigned char :1;
};
struct {
unsigned char :1;
unsigned char :1;
unsigned char GO_DONE:1;
unsigned char :1;
unsigned char :1;
unsigned char :1;
unsigned char :1;
unsigned char :1;
};
} __ADCON0_bits_t;
extern volatile __ADCON0_bits_t __at(ADCON0_ADDR) ADCON0_bits;
#define ADON ADCON0_bits.ADON
#define GO ADCON0_bits.GO
#define NOT_DONE ADCON0_bits.NOT_DONE
#define GO_DONE ADCON0_bits.GO_DONE
#define CHS0 ADCON0_bits.CHS0
#define CHS1 ADCON0_bits.CHS1
#define CHS2 ADCON0_bits.CHS2
#define ADCS0 ADCON0_bits.ADCS0
#define ADCS1 ADCON0_bits.ADCS1
// ----- ADCON1 bits --------------------
typedef union {
struct {
unsigned char PCFG0:1;
unsigned char PCFG1:1;
unsigned char PCFG2:1;
unsigned char :1;
unsigned char :1;
unsigned char :1;
unsigned char :1;
unsigned char :1;
};
} __ADCON1_bits_t;
extern volatile __ADCON1_bits_t __at(ADCON1_ADDR) ADCON1_bits;
#define PCFG0 ADCON1_bits.PCFG0
#define PCFG1 ADCON1_bits.PCFG1
#define PCFG2 ADCON1_bits.PCFG2
// ----- CCP1CON bits --------------------
typedef union {
struct {
unsigned char CCP1M0:1;
unsigned char CCP1M1:1;
unsigned char CCP1M2:1;
unsigned char CCP1M3:1;
unsigned char CCP1Y:1;
unsigned char CCP1X:1;
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