📄 pic16f687.h
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//
// Register Declarations for Microchip 16F687 Processor
//
//
// This header file was automatically generated by:
//
// inc2h.pl V1.6
//
// Copyright (c) 2002, Kevin L. Pauba, All Rights Reserved
//
// SDCC is licensed under the GNU Public license (GPL) v2. Note that
// this license covers the code to the compiler and other executables,
// but explicitly does not cover any code or objects generated by sdcc.
// We have not yet decided on a license for the run time libraries, but
// it will not put any requirements on code linked against it. See:
//
// http://www.gnu.org/copyleft/gpl/html
//
// See http://sdcc.sourceforge.net/ for the latest information on sdcc.
//
//
#ifndef P16F687_H
#define P16F687_H
//
// Register addresses.
//
#define INDF_ADDR 0x0000
#define TMR0_ADDR 0x0001
#define PCL_ADDR 0x0002
#define STATUS_ADDR 0x0003
#define FSR_ADDR 0x0004
#define PORTA_ADDR 0x0005
#define PORTB_ADDR 0x0006
#define PORTC_ADDR 0x0007
#define PCLATH_ADDR 0x000A
#define INTCON_ADDR 0x000B
#define PIR1_ADDR 0x000C
#define PIR2_ADDR 0x000D
#define TMR1L_ADDR 0x000E
#define TMR1H_ADDR 0x000F
#define T1CON_ADDR 0x0010
#define SSPBUF_ADDR 0x0013
#define SSPCON_ADDR 0x0014
#define RCSTA_ADDR 0x0018
#define TXREG_ADDR 0x0019
#define RCREG_ADDR 0x001A
#define ADRESH_ADDR 0x001E
#define ADCON0_ADDR 0x001F
#define OPTION_REG_ADDR 0x0081
#define TRISA_ADDR 0x0085
#define TRISB_ADDR 0x0086
#define TRISC_ADDR 0x0087
#define PIE1_ADDR 0x008C
#define PIE2_ADDR 0x008D
#define PCON_ADDR 0x008E
#define OSCCON_ADDR 0x008F
#define OSCTUNE_ADDR 0x0090
#define SSPADD_ADDR 0x0093
#define MSK_ADDR 0x0093
#define SSPMSK_ADDR 0x0093
#define SSPSTAT_ADDR 0x0094
#define WPU_ADDR 0x0095
#define WPUA_ADDR 0x0095
#define IOC_ADDR 0x0096
#define IOCA_ADDR 0x0096
#define WDTCON_ADDR 0x0097
#define TXSTA_ADDR 0x0098
#define SPBRG_ADDR 0x0099
#define SPBRGH_ADDR 0x009A
#define BAUDCTL_ADDR 0x009B
#define ADRESL_ADDR 0x009E
#define ADCON1_ADDR 0x009F
#define EEDATA_ADDR 0x010C
#define EEADR_ADDR 0x010D
#define EEDATH_ADDR 0x010E
#define EEADRH_ADDR 0x010F
#define WPUB_ADDR 0x0115
#define IOCB_ADDR 0x0116
#define VRCON_ADDR 0x0118
#define CM1CON0_ADDR 0x0119
#define CM2CON0_ADDR 0x011A
#define CM2CON1_ADDR 0x011B
#define ANSEL_ADDR 0x011E
#define ANSELH_ADDR 0x011F
#define EECON1_ADDR 0x018C
#define EECON2_ADDR 0x018D
#define SRCON_ADDR 0x019E
//
// Memory organization.
//
#pragma memmap INDF_ADDR INDF_ADDR SFR 0x000 // INDF
#pragma memmap TMR0_ADDR TMR0_ADDR SFR 0x000 // TMR0
#pragma memmap PCL_ADDR PCL_ADDR SFR 0x000 // PCL
#pragma memmap STATUS_ADDR STATUS_ADDR SFR 0x000 // STATUS
#pragma memmap FSR_ADDR FSR_ADDR SFR 0x000 // FSR
#pragma memmap PORTA_ADDR PORTA_ADDR SFR 0x000 // PORTA
#pragma memmap PORTB_ADDR PORTB_ADDR SFR 0x000 // PORTB
#pragma memmap PORTC_ADDR PORTC_ADDR SFR 0x000 // PORTC
#pragma memmap PCLATH_ADDR PCLATH_ADDR SFR 0x000 // PCLATH
#pragma memmap INTCON_ADDR INTCON_ADDR SFR 0x000 // INTCON
#pragma memmap PIR1_ADDR PIR1_ADDR SFR 0x000 // PIR1
#pragma memmap PIR2_ADDR PIR2_ADDR SFR 0x000 // PIR2
#pragma memmap TMR1L_ADDR TMR1L_ADDR SFR 0x000 // TMR1L
#pragma memmap TMR1H_ADDR TMR1H_ADDR SFR 0x000 // TMR1H
#pragma memmap T1CON_ADDR T1CON_ADDR SFR 0x000 // T1CON
#pragma memmap SSPBUF_ADDR SSPBUF_ADDR SFR 0x000 // SSPBUF
#pragma memmap SSPCON_ADDR SSPCON_ADDR SFR 0x000 // SSPCON
#pragma memmap RCSTA_ADDR RCSTA_ADDR SFR 0x000 // RCSTA
#pragma memmap TXREG_ADDR TXREG_ADDR SFR 0x000 // TXREG
#pragma memmap RCREG_ADDR RCREG_ADDR SFR 0x000 // RCREG
#pragma memmap ADRESH_ADDR ADRESH_ADDR SFR 0x000 // ADRESH
#pragma memmap ADCON0_ADDR ADCON0_ADDR SFR 0x000 // ADCON0
#pragma memmap OPTION_REG_ADDR OPTION_REG_ADDR SFR 0x000 // OPTION_REG
#pragma memmap TRISA_ADDR TRISA_ADDR SFR 0x000 // TRISA
#pragma memmap TRISB_ADDR TRISB_ADDR SFR 0x000 // TRISB
#pragma memmap TRISC_ADDR TRISC_ADDR SFR 0x000 // TRISC
#pragma memmap PIE1_ADDR PIE1_ADDR SFR 0x000 // PIE1
#pragma memmap PIE2_ADDR PIE2_ADDR SFR 0x000 // PIE2
#pragma memmap PCON_ADDR PCON_ADDR SFR 0x000 // PCON
#pragma memmap OSCCON_ADDR OSCCON_ADDR SFR 0x000 // OSCCON
#pragma memmap OSCTUNE_ADDR OSCTUNE_ADDR SFR 0x000 // OSCTUNE
#pragma memmap SSPADD_ADDR SSPADD_ADDR SFR 0x000 // SSPADD
#pragma memmap MSK_ADDR MSK_ADDR SFR 0x000 // MSK
#pragma memmap SSPMSK_ADDR SSPMSK_ADDR SFR 0x000 // SSPMSK
#pragma memmap SSPSTAT_ADDR SSPSTAT_ADDR SFR 0x000 // SSPSTAT
#pragma memmap WPU_ADDR WPU_ADDR SFR 0x000 // WPU
#pragma memmap WPUA_ADDR WPUA_ADDR SFR 0x000 // WPUA
#pragma memmap IOC_ADDR IOC_ADDR SFR 0x000 // IOC
#pragma memmap IOCA_ADDR IOCA_ADDR SFR 0x000 // IOCA
#pragma memmap WDTCON_ADDR WDTCON_ADDR SFR 0x000 // WDTCON
#pragma memmap TXSTA_ADDR TXSTA_ADDR SFR 0x000 // TXSTA
#pragma memmap SPBRG_ADDR SPBRG_ADDR SFR 0x000 // SPBRG
#pragma memmap SPBRGH_ADDR SPBRGH_ADDR SFR 0x000 // SPBRGH
#pragma memmap BAUDCTL_ADDR BAUDCTL_ADDR SFR 0x000 // BAUDCTL
#pragma memmap ADRESL_ADDR ADRESL_ADDR SFR 0x000 // ADRESL
#pragma memmap ADCON1_ADDR ADCON1_ADDR SFR 0x000 // ADCON1
#pragma memmap EEDATA_ADDR EEDATA_ADDR SFR 0x000 // EEDATA
#pragma memmap EEADR_ADDR EEADR_ADDR SFR 0x000 // EEADR
#pragma memmap EEDATH_ADDR EEDATH_ADDR SFR 0x000 // EEDATH
#pragma memmap EEADRH_ADDR EEADRH_ADDR SFR 0x000 // EEADRH
#pragma memmap WPUB_ADDR WPUB_ADDR SFR 0x000 // WPUB
#pragma memmap IOCB_ADDR IOCB_ADDR SFR 0x000 // IOCB
#pragma memmap VRCON_ADDR VRCON_ADDR SFR 0x000 // VRCON
#pragma memmap CM1CON0_ADDR CM1CON0_ADDR SFR 0x000 // CM1CON0
#pragma memmap CM2CON0_ADDR CM2CON0_ADDR SFR 0x000 // CM2CON0
#pragma memmap CM2CON1_ADDR CM2CON1_ADDR SFR 0x000 // CM2CON1
#pragma memmap ANSEL_ADDR ANSEL_ADDR SFR 0x000 // ANSEL
#pragma memmap ANSELH_ADDR ANSELH_ADDR SFR 0x000 // ANSELH
#pragma memmap EECON1_ADDR EECON1_ADDR SFR 0x000 // EECON1
#pragma memmap EECON2_ADDR EECON2_ADDR SFR 0x000 // EECON2
#pragma memmap SRCON_ADDR SRCON_ADDR SFR 0x000 // SRCON
// LIST
// P16F687.INC Standard Header File, Version 1.00 Microchip Technology, Inc.
// NOLIST
// This header file defines configurations, registers, and other useful bits of
// information for the PIC16F687 microcontroller. These names are taken to match
// the data sheets as closely as possible.
// Note that the processor must be selected before this file is
// included. The processor may be selected the following ways:
// 1. Command line switch:
// C:\ MPASM MYFILE.ASM /PIC16F687
// 2. LIST directive in the source file
// LIST P=PIC16F687
// 3. Processor Type entry in the MPASM full-screen interface
//==========================================================================
//
// Revision History
//
//==========================================================================
//1.00 10/12/04 Original
//==========================================================================
//
// Verify Processor
//
//==========================================================================
// IFNDEF __16F687
// MESSG "Processor-header file mismatch. Verify selected processor."
// ENDIF
//==========================================================================
//
// Register Definitions
//
//==========================================================================
#define W 0x0000
#define F 0x0001
//----- Register Files------------------------------------------------------
extern __data __at (INDF_ADDR) volatile char INDF;
extern __sfr __at (TMR0_ADDR) TMR0;
extern __data __at (PCL_ADDR) volatile char PCL;
extern __sfr __at (STATUS_ADDR) STATUS;
extern __sfr __at (FSR_ADDR) FSR;
extern __sfr __at (PORTA_ADDR) PORTA;
extern __sfr __at (PORTB_ADDR) PORTB;
extern __sfr __at (PORTC_ADDR) PORTC;
extern __sfr __at (PCLATH_ADDR) PCLATH;
extern __sfr __at (INTCON_ADDR) INTCON;
extern __sfr __at (PIR1_ADDR) PIR1;
extern __sfr __at (PIR2_ADDR) PIR2;
extern __sfr __at (TMR1L_ADDR) TMR1L;
extern __sfr __at (TMR1H_ADDR) TMR1H;
extern __sfr __at (T1CON_ADDR) T1CON;
extern __sfr __at (SSPBUF_ADDR) SSPBUF;
extern __sfr __at (SSPCON_ADDR) SSPCON;
extern __sfr __at (RCSTA_ADDR) RCSTA;
extern __sfr __at (TXREG_ADDR) TXREG;
extern __sfr __at (RCREG_ADDR) RCREG;
extern __sfr __at (ADRESH_ADDR) ADRESH;
extern __sfr __at (ADCON0_ADDR) ADCON0;
extern __sfr __at (OPTION_REG_ADDR) OPTION_REG;
extern __sfr __at (TRISA_ADDR) TRISA;
extern __sfr __at (TRISB_ADDR) TRISB;
extern __sfr __at (TRISC_ADDR) TRISC;
extern __sfr __at (PIE1_ADDR) PIE1;
extern __sfr __at (PIE2_ADDR) PIE2;
extern __sfr __at (PCON_ADDR) PCON;
extern __sfr __at (OSCCON_ADDR) OSCCON;
extern __sfr __at (OSCTUNE_ADDR) OSCTUNE;
extern __sfr __at (SSPADD_ADDR) SSPADD;
extern __sfr __at (MSK_ADDR) MSK;
extern __sfr __at (SSPMSK_ADDR) SSPMSK;
extern __sfr __at (SSPSTAT_ADDR) SSPSTAT;
extern __sfr __at (WPU_ADDR) WPU;
extern __sfr __at (WPUA_ADDR) WPUA;
extern __sfr __at (IOC_ADDR) IOC;
extern __sfr __at (IOCA_ADDR) IOCA;
extern __sfr __at (WDTCON_ADDR) WDTCON;
extern __sfr __at (TXSTA_ADDR) TXSTA;
extern __sfr __at (SPBRG_ADDR) SPBRG;
extern __sfr __at (SPBRGH_ADDR) SPBRGH;
extern __sfr __at (BAUDCTL_ADDR) BAUDCTL;
extern __sfr __at (ADRESL_ADDR) ADRESL;
extern __sfr __at (ADCON1_ADDR) ADCON1;
extern __sfr __at (EEDATA_ADDR) EEDATA;
extern __sfr __at (EEADR_ADDR) EEADR;
extern __sfr __at (EEDATH_ADDR) EEDATH;
extern __sfr __at (EEADRH_ADDR) EEADRH;
extern __sfr __at (WPUB_ADDR) WPUB;
extern __sfr __at (IOCB_ADDR) IOCB;
extern __sfr __at (VRCON_ADDR) VRCON;
extern __sfr __at (CM1CON0_ADDR) CM1CON0;
extern __sfr __at (CM2CON0_ADDR) CM2CON0;
extern __sfr __at (CM2CON1_ADDR) CM2CON1;
extern __sfr __at (ANSEL_ADDR) ANSEL;
extern __sfr __at (ANSELH_ADDR) ANSELH;
extern __sfr __at (EECON1_ADDR) EECON1;
extern __sfr __at (EECON2_ADDR) EECON2;
extern __sfr __at (SRCON_ADDR) SRCON;
//----- BANK 0 REGISTER DEFINITIONS ----------------------------------------
//----- STATUS Bits --------------------------------------------------------
//----- INTCON Bits --------------------------------------------------------
//----- PIR1 Bits ----------------------------------------------------------
//----- PIR2 Bits ----------------------------------------------------------
//----- T1CON Bits ---------------------------------------------------------
//----- SSPCON Bits -------------------------------------------------------
//----- RCSTA Bits ---------------------------------------------------------
//----- ADCON0 Bits --------------------------------------------------------
//----- BANK 1 REGISTER DEFINITIONS ----------------------------------------
//----- OPTION Bits --------------------------------------------------------
//----- TRISA Bits --------------------------------------------------------
//----- TRISB Bits --------------------------------------------------------
//----- TRISC Bits --------------------------------------------------------
//----- PIE1 Bits ----------------------------------------------------------
//----- PIE2 Bits ----------------------------------------------------------
//----- PCON Bits ----------------------------------------------------------
//----- OSCCON Bits --------------------------------------------------------
//----- OSCTUNE Bits -------------------------------------------------------
//----- SSPSTAT Bits --------------------------------------------------------
//----- WPUA --------------------------------------------------------------
//----- IOC --------------------------------------------------------------
//----- IOCA --------------------------------------------------------------
//----- WDTCON Bits --------------------------------------------------------
//----- TXSTA Bits -------------------------------------------------------
//----- SPBRG Bits -------------------------------------------------------
//----- SPBRGH Bits -------------------------------------------------------
//----- BAUDCTL Bits -------------------------------------------------------
//----- ADCON1 -------------------------------------------------------------
//----- BANK 2 REGISTER DEFINITIONS ----------------------------------------
//----- WPUB Bits ----------------------------------------------------------
//----- IOCB --------------------------------------------------------------
//----- VRCON Bits ---------------------------------------------------------
//----- CM1CON0 Bits -------------------------------------------------------
//----- CM2CON0 Bits -------------------------------------------------------
//----- CM2CON1 Bits -------------------------------------------------------
//----- ANSEL --------------------------------------------------------------
//----- BANK 3 REGISTER DEFINITIONS ----------------------------------------
//----- EECON1 -------------------------------------------------------------
//----- SRCON ---------------------------------------------------------------
//==========================================================================
//
// RAM Definition
//
//==========================================================================
// __MAXRAM H'1FF'
// __BADRAM H'08'-H'09', H'11'-H'12', H'15'-H'17', H'1B'- H'1D'
// __BADRAM H'88'-H'89', H'91'-H'92', H'9C'-H'9D', H'C0'-H'EF'
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