📄 pic24hj64gp210.h
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/*
* Header file for the Pic24HJ64GP210 microcontroller.
*/
#ifndef __PIC24HJ64GP210_H
#define __PIC24HJ64GP210_H
//------------------------------------------------------------------------------
// Special Function Registers
//------------------------------------------------------------------------------
static volatile unsigned int WREG0 @ 0x0;
static volatile unsigned int WREG1 @ 0x2;
static volatile unsigned int WREG2 @ 0x4;
static volatile unsigned int WREG3 @ 0x6;
static volatile unsigned int WREG4 @ 0x8;
static volatile unsigned int WREG5 @ 0xA;
static volatile unsigned int WREG6 @ 0xC;
static volatile unsigned int WREG7 @ 0xE;
static volatile unsigned int WREG8 @ 0x10;
static volatile unsigned int WREG9 @ 0x12;
static volatile unsigned int WREG10 @ 0x14;
static volatile unsigned int WREG11 @ 0x16;
static volatile unsigned int WREG12 @ 0x18;
static volatile unsigned int WREG13 @ 0x1A;
static volatile unsigned int WREG14 @ 0x1C;
static volatile unsigned int WREG15 @ 0x1E;
static volatile unsigned int SPLIM @ 0x20;
static volatile unsigned int PCL @ 0x2E;
static volatile unsigned int PCH @ 0x30;
static volatile unsigned int TBLPAG @ 0x32;
static volatile unsigned int PSVPAG @ 0x34;
static volatile unsigned int RCOUNT @ 0x36;
static volatile unsigned int SR @ 0x42;
static volatile bit C @ ((unsigned)&SR*8)+0;
static volatile bit Z @ ((unsigned)&SR*8)+1;
static volatile bit OV @ ((unsigned)&SR*8)+2;
static volatile bit N @ ((unsigned)&SR*8)+3;
static volatile bit RA @ ((unsigned)&SR*8)+4;
static volatile bit IPL0 @ ((unsigned)&SR*8)+5;
static volatile bit IPL1 @ ((unsigned)&SR*8)+6;
static volatile bit IPL2 @ ((unsigned)&SR*8)+7;
static volatile bit DC @ ((unsigned)&SR*8)+8;
/* Microchip compatible bit field */
static volatile struct {
unsigned : 1;
unsigned : 1;
unsigned : 1;
unsigned : 1;
unsigned : 1;
unsigned : 1;
unsigned : 1;
volatile unsigned DC : 1;
volatile unsigned IPL : 3;
volatile unsigned RA : 1;
volatile unsigned N : 1;
volatile unsigned OV : 1;
volatile unsigned Z : 1;
volatile unsigned C : 1;
} SRbits @ 0x42;
static volatile unsigned int CORCON @ 0x44;
static volatile bit PSV @ ((unsigned)&CORCON*8)+2;
static volatile bit IPL3 @ ((unsigned)&CORCON*8)+3;
/* Microchip compatible bit field */
static volatile struct {
unsigned : 1;
unsigned : 1;
unsigned : 1;
unsigned : 1;
unsigned : 1;
unsigned : 1;
unsigned : 1;
unsigned : 1;
unsigned : 1;
unsigned : 1;
unsigned : 1;
unsigned : 1;
volatile unsigned IPL3 : 1;
volatile unsigned PSV : 1;
unsigned : 1;
unsigned : 1;
} CORCONbits @ 0x44;
static volatile unsigned int DISICNT @ 0x52;
static volatile unsigned int CNEN1 @ 0x60;
static volatile bit CN0IE @ ((unsigned)&CNEN1*8)+0;
static volatile bit CN1IE @ ((unsigned)&CNEN1*8)+1;
static volatile bit CN2IE @ ((unsigned)&CNEN1*8)+2;
static volatile bit CN3IE @ ((unsigned)&CNEN1*8)+3;
static volatile bit CN4IE @ ((unsigned)&CNEN1*8)+4;
static volatile bit CN5IE @ ((unsigned)&CNEN1*8)+5;
static volatile bit CN6IE @ ((unsigned)&CNEN1*8)+6;
static volatile bit CN7IE @ ((unsigned)&CNEN1*8)+7;
static volatile bit CN8IE @ ((unsigned)&CNEN1*8)+8;
static volatile bit CN9IE @ ((unsigned)&CNEN1*8)+9;
static volatile bit CN10IE @ ((unsigned)&CNEN1*8)+10;
static volatile bit CN11IE @ ((unsigned)&CNEN1*8)+11;
static volatile bit CN12IE @ ((unsigned)&CNEN1*8)+12;
static volatile bit CN13IE @ ((unsigned)&CNEN1*8)+13;
static volatile bit CN14IE @ ((unsigned)&CNEN1*8)+14;
static volatile bit CN15IE @ ((unsigned)&CNEN1*8)+15;
/* Microchip compatible bit field */
static volatile struct {
volatile unsigned CN15IE : 1;
volatile unsigned CN14IE : 1;
volatile unsigned CN13IE : 1;
volatile unsigned CN12IE : 1;
volatile unsigned CN11IE : 1;
volatile unsigned CN10IE : 1;
volatile unsigned CN9IE : 1;
volatile unsigned CN8IE : 1;
volatile unsigned CN7IE : 1;
volatile unsigned CN6IE : 1;
volatile unsigned CN5IE : 1;
volatile unsigned CN4IE : 1;
volatile unsigned CN3IE : 1;
volatile unsigned CN2IE : 1;
volatile unsigned CN1IE : 1;
volatile unsigned CN0IE : 1;
} CNEN1bits @ 0x60;
static volatile unsigned int CNEN2 @ 0x62;
static volatile bit CN16IE @ ((unsigned)&CNEN2*8)+0;
static volatile bit CN17IE @ ((unsigned)&CNEN2*8)+1;
static volatile bit CN18IE @ ((unsigned)&CNEN2*8)+2;
static volatile bit CN19IE @ ((unsigned)&CNEN2*8)+3;
static volatile bit CN20IE @ ((unsigned)&CNEN2*8)+4;
static volatile bit CN21IE @ ((unsigned)&CNEN2*8)+5;
static volatile bit CN22IE @ ((unsigned)&CNEN2*8)+6;
static volatile bit CN23IE @ ((unsigned)&CNEN2*8)+7;
/* Microchip compatible bit field */
static volatile struct {
unsigned : 1;
unsigned : 1;
unsigned : 1;
unsigned : 1;
unsigned : 1;
unsigned : 1;
unsigned : 1;
unsigned : 1;
volatile unsigned CN23IE : 1;
volatile unsigned CN22IE : 1;
volatile unsigned CN21IE : 1;
volatile unsigned CN20IE : 1;
volatile unsigned CN19IE : 1;
volatile unsigned CN18IE : 1;
volatile unsigned CN17IE : 1;
volatile unsigned CN16IE : 1;
} CNEN2bits @ 0x62;
static volatile unsigned int CNPU1 @ 0x68;
static volatile bit CN0PUE @ ((unsigned)&CNPU1*8)+0;
static volatile bit CN1PUE @ ((unsigned)&CNPU1*8)+1;
static volatile bit CN2PUE @ ((unsigned)&CNPU1*8)+2;
static volatile bit CN3PUE @ ((unsigned)&CNPU1*8)+3;
static volatile bit CN4PUE @ ((unsigned)&CNPU1*8)+4;
static volatile bit CN5PUE @ ((unsigned)&CNPU1*8)+5;
static volatile bit CN6PUE @ ((unsigned)&CNPU1*8)+6;
static volatile bit CN7PUE @ ((unsigned)&CNPU1*8)+7;
static volatile bit CN8PUE @ ((unsigned)&CNPU1*8)+8;
static volatile bit CN9PUE @ ((unsigned)&CNPU1*8)+9;
static volatile bit CN10PUE @ ((unsigned)&CNPU1*8)+10;
static volatile bit CN11PUE @ ((unsigned)&CNPU1*8)+11;
static volatile bit CN12PUE @ ((unsigned)&CNPU1*8)+12;
static volatile bit CN13PUE @ ((unsigned)&CNPU1*8)+13;
static volatile bit CN14PUE @ ((unsigned)&CNPU1*8)+14;
static volatile bit CN15PUE @ ((unsigned)&CNPU1*8)+15;
/* Microchip compatible bit field */
static volatile struct {
volatile unsigned CN15PUE : 1;
volatile unsigned CN14PUE : 1;
volatile unsigned CN13PUE : 1;
volatile unsigned CN12PUE : 1;
volatile unsigned CN11PUE : 1;
volatile unsigned CN10PUE : 1;
volatile unsigned CN9PUE : 1;
volatile unsigned CN8PUE : 1;
volatile unsigned CN7PUE : 1;
volatile unsigned CN6PUE : 1;
volatile unsigned CN5PUE : 1;
volatile unsigned CN4PUE : 1;
volatile unsigned CN3PUE : 1;
volatile unsigned CN2PUE : 1;
volatile unsigned CN1PUE : 1;
volatile unsigned CN0PUE : 1;
} CNPU1bits @ 0x68;
static volatile unsigned int CNPU2 @ 0x6A;
static volatile bit CN16PUE @ ((unsigned)&CNPU2*8)+0;
static volatile bit CN17PUE @ ((unsigned)&CNPU2*8)+1;
static volatile bit CN18PUE @ ((unsigned)&CNPU2*8)+2;
static volatile bit CN19PUE @ ((unsigned)&CNPU2*8)+3;
static volatile bit CN20PUE @ ((unsigned)&CNPU2*8)+4;
static volatile bit CN21PUE @ ((unsigned)&CNPU2*8)+5;
static volatile bit CN22PUE @ ((unsigned)&CNPU2*8)+6;
static volatile bit CN23PUE @ ((unsigned)&CNPU2*8)+7;
/* Microchip compatible bit field */
static volatile struct {
unsigned : 1;
unsigned : 1;
unsigned : 1;
unsigned : 1;
unsigned : 1;
unsigned : 1;
unsigned : 1;
unsigned : 1;
volatile unsigned CN23PUE : 1;
volatile unsigned CN22PUE : 1;
volatile unsigned CN21PUE : 1;
volatile unsigned CN20PUE : 1;
volatile unsigned CN19PUE : 1;
volatile unsigned CN18PUE : 1;
volatile unsigned CN17PUE : 1;
volatile unsigned CN16PUE : 1;
} CNPU2bits @ 0x6A;
static volatile unsigned int INTCON1 @ 0x80;
static volatile bit OSCFAIL @ ((unsigned)&INTCON1*8)+1;
static volatile bit STKERR @ ((unsigned)&INTCON1*8)+2;
static volatile bit ADDRERR @ ((unsigned)&INTCON1*8)+3;
static volatile bit MATHERR @ ((unsigned)&INTCON1*8)+4;
static volatile bit DMAC @ ((unsigned)&INTCON1*8)+5;
static volatile bit NSTDIS @ ((unsigned)&INTCON1*8)+15;
/* Microchip compatible bit field */
static volatile struct {
volatile unsigned NSTDIS : 1;
unsigned : 1;
unsigned : 1;
unsigned : 1;
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