at91twi.h

AT91RM9200工程评估板的CPU源代码

#ifndef _AT91_TWI_DEFINE_HEADER
#define _AT91_TWI_DEFINE_HEADER


#define TWI_BASE_ADDR	0xFFFB8000
#define EEPROM_PAGE_SIZE	32
#define EEPROM_MAX_SIZE		8192
#define IICCLK				50000


#ifndef _ASMLANGUAGE
typedef struct _TWI_S
{
	AT91_REG	 TWI_CR; 		/* Control Register						*/
	AT91_REG	 TWI_MMR; 		/* Master Mode Register                 */
	AT91_REG	 TWI_SMR; 		/* Slave Mode Register                  */
	AT91_REG	 TWI_IADR; 		/* Internal Address Register            */
	AT91_REG	 TWI_CWGR; 		/* Clock Waveform Generator Register    */
	AT91_REG	 Reserved0[3]; 	/*                                      */
	AT91_REG	 TWI_SR; 		/* Status Register                      */
	AT91_REG	 TWI_IER; 		/* Interrupt Enable Register            */
	AT91_REG	 TWI_IDR; 		/* Interrupt Disable Register           */
	AT91_REG	 TWI_IMR; 		/* Interrupt Mask Register              */
	AT91_REG	 TWI_RHR; 		/* Receive Holding Register             */
	AT91_REG	 TWI_THR; 		/* Transmit Holding Register            */
}TWI_S;


/* device and channel structures 
typedef struct
{
	UINT8 slaveAddress;
	UINT8 writeAddrMSB; 
	UINT8 writeAddrLSB;
	UINT32 dataSize;
	UINT8 pageBuff [EEPROM_PAGE_SIZE];
	UINT32 byteWriteCount;
	UINT32 totalBytesWritten;
	UINT8 flag;
	SEM_ID endofWriteSemID;
} IIC_TXMIT;

typedef struct
{
	UINT8 slaveAddress;
	UINT8 readAddrMSB; 
	UINT8 readAddrLSB;
	UINT32 dataSize;
	UINT8 *rxBuff;
	UINT32 byteReadCount;
	UINT32 totalBytesRead;
	UINT8 flag;
	SEM_ID endofReadSemID;
} IIC_RCV;

typedef struct
{
     register addresses 
	volatile UINT32 *iiccon;            
	volatile UINT32 *iicbuf;            
	volatile UINT32 *iicps;            
	volatile UINT32 *iiccnt; 
     misc 
	IIC_TXMIT	IIC_Txmit;
	IIC_RCV		IIC_Rcv;
	SEM_ID IICSemID;
	int int_vec;
	int sclk;
} AT91_TWI;

*/
#endif



/* definitions */
/*Reset values for Registers*/
#define TWI_CR_START			(1<<0)
#define TWI_CR_STOP				(1<<1)
#define TWI_CR_MSEN				(1<<2)
#define TWI_CR_MSDIS			(1<<3)
#define TWI_CR_SWRST			(1<<7)

#define TWI_MMR_ADSIZE_NONE		(0<<8)
#define TWI_MMR_ADSIZE_8BIT		(1<<8)
#define TWI_MMR_ADSIZE_16BIT	(2<<8)
#define TWI_MMR_ADSIZE_24BIT	(3<<8)

#define TWI_MMR_MREAD			(1<<12)
#define TWI_MMR_DADR			(0x7f<<16)

#define TWI_SR_TXCOMP			(1<<0)
#define TWI_SR_RXRDY			(1<<1)
#define TWI_SR_TXRDY			(1<<2)
#define TWI_SR_OVRE				(1<<6)
#define TWI_SR_UNRE				(1<<7)
#define TWI_SR_NACK				(1<<8)

#define TWI_IE_DR_TXCOMP			(1<<0)
#define TWI_IE_DR_RXRDY				(1<<1)
#define TWI_IE_DR_TXRDY				(1<<2)
#define TWI_IE_DR_OVRE				(1<<6)
#define TWI_IE_DR_UNRE				(1<<7)
#define TWI_IE_DR_NACK				(1<<8)


#endif /*_AT91_TWI_DEFINE_HEADER*/