proll.patch

qemu虚拟机代码

+t_badd4:BAD_TRAP(0xd4) BAD_TRAP(0xd5) BAD_TRAP(0xd6) BAD_TRAP(0xd7)
+ BAD_TRAP(0xd8) BAD_TRAP(0xd9) BAD_TRAP(0xda) BAD_TRAP(0xdb)
+ BAD_TRAP(0xdc) BAD_TRAP(0xdd) BAD_TRAP(0xde) BAD_TRAP(0xdf)
+ BAD_TRAP(0xe0) BAD_TRAP(0xe1) BAD_TRAP(0xe2) BAD_TRAP(0xe3)
+ BAD_TRAP(0xe4) BAD_TRAP(0xe5) BAD_TRAP(0xe6) BAD_TRAP(0xe7)
+t_bade8:BAD_TRAP(0xe8) BAD_TRAP(0xe9) BAD_TRAP(0xea) BAD_TRAP(0xeb)
+ BAD_TRAP(0xec) BAD_TRAP(0xed) BAD_TRAP(0xee) BAD_TRAP(0xef)
+ BAD_TRAP(0xf0) BAD_TRAP(0xf1) BAD_TRAP(0xf2) BAD_TRAP(0xf3)
+ BAD_TRAP(0xf4) BAD_TRAP(0xf5) BAD_TRAP(0xf6) BAD_TRAP(0xf7)
+ BAD_TRAP(0xf8) BAD_TRAP(0xf9) BAD_TRAP(0xfa) BAD_TRAP(0xfb)
+t_badfc:BAD_TRAP(0xfc) BAD_TRAP(0xfd)
+dbtrap:	BAD_TRAP(0xfe)                      /* Debugger/PROM breakpoint #1   */
+dbtrap2:BAD_TRAP(0xff)                      /* Debugger/PROM breakpoint #2   */	
+
+stub_trap:
+   set (PHYS_JJ_TCX_FB + 0xbf0), %g5	/* 2 cells from side */
+   set 0x00ffffff, %g4
+   sta %g4, [%g5] ASI_M_BYPASS
+1:	ba 1b; nop
+
+	.section ".bss"
+	.align 8
+bss_start:
+	.align	0x1000		! PAGE_SIZE
+	.globl C_LABEL(bootup_user_stack)
+        .type   bootup_user_stack,#object
+        .size   bootup_user_stack,0x2000
+C_LABEL(bootup_user_stack):		.skip 0x2000
+
+	.section ".text"
+	.register %g2, #scratch
+	.register %g3, #scratch
+	.register %g6, #scratch
+	.register %g7, #scratch
+
+goprol:
+	! %g1 contains end of memory
+	set	PHYS_JJ_EEPROM + 0x30, %g1
+	lda	[%g1] ASI_M_BYPASS, %g1
+	! map PROLDATA to PROLBASE+PROLSIZE to end of ram
+	set	PROLSIZE+0x1000-PROLDATA+PROLBASE, %g2	! add 0x1000 for temp tables
+	sub	%g1, %g2, %g2			! start of private memory
+	srl	%g2, 0x4, %g7			! ctx table at s+0x0
+	add	%g2, 0x400, %g3			! l1 table at s+0x400
+	srl	%g3, 0x4, %g3
+	or	%g3, 0x1, %g3
+	sta	%g3, [%g2] ASI_M_BYPASS
+	add	%g2, 0x400, %g2			! s+0x400
+	add	%g2, 0x800, %g3			! l2 table for ram (00xxxxxx) at s+0x800
+	srl	%g3, 0x4, %g3
+	or	%g3, 0x1, %g3
+	sta	%g3, [%g2] ASI_M_BYPASS
+	add	%g2, 0x500, %g3			! l2 table for rom (ffxxxxxx) at s+0x900
+	add	%g2, 0x3fc, %g2			! s+0x7fc
+	srl	%g3, 0x4, %g3
+	or	%g3, 0x1, %g3
+	sta	%g3, [%g2] ASI_M_BYPASS
+	add	%g2, 0x4, %g2			! s+0x800
+	set	((7 << 2) | 2), %g3		! 7 = U: --- S: RWX (main memory)
+	sta	%g3, [%g2] ASI_M_BYPASS
+	add	%g2, 0x200, %g3			! l3 table for rom at s+0xa00
+	add	%g2, 0x1d0, %g2			! s+0x9d0
+	srl	%g3, 0x4, %g3
+	or	%g3, 0x1, %g3
+	sta	%g3, [%g2] ASI_M_BYPASS
+	add	%g2, 0x30, %g2			! s+0xa00
+
+	set	PROLBASE, %g3
+	set	0x1000, %g5
+	set	(PROLDATA-PROLBASE)/0x1000, %g6 ! # of .text pages
+1:	srl	%g3, 0x4, %g4
+	or	%g4, ((7 << 2) | 2), %g4	! 4 = U: --X S: --X (rom, execute only)
+	sta	%g4, [%g2] ASI_M_BYPASS
+	add	%g2, 4, %g2
+	add	%g3, %g5, %g3
+	deccc	%g6
+	bne	1b
+	 nop
+#if 0	
+	set	(PROLDATA-PROLRODATA)/0x1000, %g6 ! # of .rodata pages
+1:	srl	%g3, 0x4, %g4
+	or	%g4, ((0 << 2) | 2), %g4	! 0 = U: R-- S: R-- (rom, read only)
+	sta	%g4, [%g2] ASI_M_BYPASS
+	add	%g2, 4, %g2
+	add	%g3, %g5, %g3
+	deccc	%g6
+	bne	1b
+	 nop
+#endif
+	set	(PROLBASE+PROLSIZE-PROLDATA)/0x1000, %g6 ! # of .bss pages
+	set	0x1000, %g4
+	sll	%g7, 0x4, %g3
+	add	%g4, %g3, %g3
+1:	srl	%g3, 0x4, %g4
+	or	%g4, ((7 << 2) | 2), %g4        ! 5 = U: R-- S: RW- (data area, read/write)
+	sta	%g4, [%g2] ASI_M_BYPASS
+	add	%g2, 4, %g2
+	add	%g3, %g5, %g3
+	deccc	%g6
+	bne	1b
+	 nop
+
+	mov	%g1, %g3
+
+	set     AC_M_CTPR, %g2
+	sta     %g7, [%g2] ASI_M_MMUREGS	! set ctx table ptr
+	set	1, %g1
+	sta     %g1, [%g0] ASI_M_MMUREGS	! enable mmu
+
+	/*
+	 * The code which enables traps is a simplified version of
+	 * kernel head.S.
+	 *
+	 * We know number of windows as 8 so we do not calculate them.
+	 * The deadwood is here for any case.
+	 */
+
+	/* Turn on Supervisor, EnableFloating, and all the PIL bits.
+	 * Also puts us in register window zero with traps off.
+	 */
+	set	(PSR_PS | PSR_S | PSR_PIL | PSR_EF), %g2
+	wr	%g2, 0x0, %psr
+	WRITE_PAUSE
+
+	/* I want a kernel stack NOW! */
+	set	C_LABEL(bootup_user_stack), %g1
+	set	(0x2000 - REGWIN_SZ), %g2
+	add	%g1, %g2, %sp
+	mov	0, %fp			/* And for good luck */
+
+	/* Zero out our BSS section. */
+	set	C_LABEL(bss_start) , %o0	! First address of BSS
+	set	C_LABEL(end) , %o1		! Last address of BSS
+	ba	2f
+	 nop
+1:
+	st	%g0, [%o0]
+2:
+	subcc	%o0, %o1, %g0
+	bl	1b
+	 add	%o0, 0x4, %o0
+
+	mov	2, %g1
+	wr	%g1, 0x0, %wim			! make window 1 invalid
+	WRITE_PAUSE
+
+#if 0
+	wr  %g0, 0x0, %wim
+	WRITE_PAUSE
+	save
+	rd  %psr, %g3
+	restore
+	and  %g3, PSR_CWP, %g3
+	add  %g3, 0x1, %g3
+#else
+	or	%g0, 8, %g3
+#endif
+
+#if 0
+	sethi	%hi( C_LABEL(cputyp) ), %o0
+	st	%g7, [%o0 + %lo( C_LABEL(cputyp) )]
+
+	sethi	%hi( C_LABEL(nwindows) ), %g4
+	st	%g3, [%g4 + %lo( C_LABEL(nwindows) )]
+
+	sub	%g3, 0x1, %g3
+	sethi	%hi( C_LABEL(nwindowsm1) ), %g4
+	st	%g3, [%g4 + %lo( C_LABEL(nwindowsm1) )]
+#endif
+
+	/* Here we go, start using Linux's trap table... */
+	set	C_LABEL(trapbase), %g3
+	wr	%g3, 0x0, %tbr
+	WRITE_PAUSE
+
+	/* Finally, turn on traps so that we can call c-code. */
+	rd	%psr, %g3
+	wr	%g3, 0x0, %psr
+	WRITE_PAUSE
+
+	wr	%g3, PSR_ET, %psr
+	WRITE_PAUSE
+
+	.globl prolmain
+	call C_LABEL(prolmain)
+	 nop
+
+3:
+	b       3b
+	 nop
+
+/*
+ * Memory access trap handler
+ *   %l0  program %psr from trap table entry
+ *   %l1  program %pc from hardware
+ *   %l2  program %npc from hardware
+ *   %l3  program %wim from trap table entry
+ *   %l4
+ *   %l5
+ *   %l6
+ *   %l7  text flag from trap table entry
+ */
+
+	.section ".text"
+	.globl srmmu_fault
+C_LABEL(srmmu_fault):
+
+	set AC_M_SFAR, %l6
+	set AC_M_SFSR, %l5
+	lda [%l6] ASI_M_MMUREGS, %l6
+	lda [%l5] ASI_M_MMUREGS, %l5
+
+	set ignore_fault, %l5
+	ld [%l5], %l5
+	subcc %l5, %g0, %g0		/* NULL pointer trap faults always */
+	be 3f
+	 nop
+	subcc %l5, %l6, %g0
+	be 2f
+	 nop
+3:
+
+   set (PHYS_JJ_TCX_FB + 0xbf0), %g5	/* 2 cells from side */
+   set 0x00ffffff, %g4
+   sta %g4, [%g5] ASI_M_BYPASS
+   add %g5, 8, %g5			/* On right side */
+   sta %g4, [%g5] ASI_M_BYPASS
+1:	ba 1b; nop
+
+2:
+	set C_LABEL(fault_ignored), %l5
+	mov 1, %l6
+	st %l6, [%l5]
+
+	/*
+	 * Skip the faulting instruction.
+	 * I think it works when next instruction is a branch even.
+	 */
+	or %l2, 0, %l1
+	add %l2, 4, %l2
+
+	wr %l0, 0, %psr
+	WRITE_PAUSE
+	jmp %l1
+	rett %l2
+
+/*
+ * Slow external versions of st_bypass and ld_bypass.
+ * rconsole.c uses inlines. We call these in places which are not speed
+ * critical, to avoid compiler bugs.
+ */
+	.globl C_LABEL(st_bypass)
+C_LABEL(st_bypass):
+	retl
+	 sta %o1, [%o0] ASI_M_BYPASS
+	.globl C_LABEL(ld_bypass)
+C_LABEL(ld_bypass):
+	retl
+	 lda [%o0] ASI_M_BYPASS, %o0
+	.globl C_LABEL(sth_bypass)
+C_LABEL(sth_bypass):
+	retl
+	 stha %o1, [%o0] ASI_M_BYPASS
+	.globl C_LABEL(ldh_bypass)
+C_LABEL(ldh_bypass):
+	retl
+	 lduha [%o0] ASI_M_BYPASS, %o0
+	.globl C_LABEL(stb_bypass)
+C_LABEL(stb_bypass):
+	retl
+	 stba %o1, [%o0] ASI_M_BYPASS
+	.globl C_LABEL(ldb_bypass)
+C_LABEL(ldb_bypass):
+	retl
+	 lduba [%o0] ASI_M_BYPASS, %o0
diff -ruN proll_18.orig/qemu/main.c proll-patch-15/qemu/main.c
--- proll_18.orig/qemu/main.c	1970-01-01 00:00:00.000000000 +0000
+++ proll-patch-15/qemu/main.c	2005-08-14 10:07:48.000000000 +0000
@@ -0,0 +1,185 @@
+/**
+ ** Proll (PROM replacement)
+ ** Copyright 1999 Pete Zaitcev
+ ** This code is licensed under GNU General Public License.
+ **/
+#include <stdarg.h>
+
+// #include <asm/contregs.h>
+#include <asi.h>
+#include "pgtsrmmu.h"
+#include "iommu.h"		/* Typical SBus IOMMU for sun4m */
+#include "phys_jj.h"
+#include "vconsole.h"
+#include "version.h"
+#include <general.h>		/* __P() */
+#include <net.h>		/* init_net() */
+#include <romlib.h>		/* we are a provider for part of this. */
+#include <netpriv.h>		/* myipaddr */
+#include <arpa.h>
+#include <system.h>		/* our own prototypes */
+
+void *init_openprom_qemu(int bankc, struct bank *bankv, unsigned hiphybas, const char *cmdline, char boot_device, int nographic);
+int vcon_zs_init(struct vconterm *t, unsigned int a0);
+int vcon_zs_write(struct vconterm *t, char *data, int leng);
+int vcon_zs_getch(struct vconterm *t);
+void esp_probe();
+int esp_boot(int unit);
+static void init_idprom(void);
+
+struct vconterm dp0;
+struct mem cmem;		/* Current memory, virtual */
+struct mem cio;			/* Current I/O space */
+struct phym pmem;		/* Current phys. mem. */
+struct iommu ciommu;		/* Our IOMMU on sun4m */
+
+static struct {
+    const char id[16];
+    unsigned int version;
+    char pad1[0x1c]; // Pad to 0x30
+    unsigned int ram_size;
+    char boot_device;
+    unsigned int load_addr, kernel_size;
+    unsigned int cmdline, cmdline_len;
+    char pad2[0x0c]; // Pad to 0x54
+    unsigned short width, height, depth;
+} *hw_idprom;
+
+int ignore_fault, fault_ignored;
+void *printk_fn, *getch_fn;
+unsigned int q_height, q_width;
+
+/*
+ */
+void prolmain()
+{
+	static char fname[14];
+	static struct banks bb;
+	unsigned int hiphybas;
+	const void *romvec;
+	unsigned int ram_size;
+	char nographic, bootdev;
+
+	nographic = ldb_bypass(PHYS_JJ_EEPROM + 0x2F);
+	if (!nographic) {
+	    q_width = ldh_bypass(PHYS_JJ_EEPROM + 0x54);
+	    q_height = ldh_bypass(PHYS_JJ_EEPROM + 0x56);
+	    vcon_init(&dp0, PHYS_JJ_TCX_FB);
+	    printk_fn = vcon_write;
+	    getch_fn = vcon_getch;
+	}
+	else {
+	    vcon_zs_init(&dp0, 0x71100004);
+	    printk_fn = vcon_zs_write;
+	    getch_fn = vcon_zs_getch;
+	}
+
+
+	printk("PROLL %s QEMU\n", PROLL_VERSION_STRING);
+	ram_size = ld_bypass(PHYS_JJ_EEPROM + 0x30);
+	printk("%d MB total\n", ram_size/(1024*1024));
+
+	bb.nbanks = 1;
+	bb.bankv[0].start = 0;
+	bb.bankv[0].length = ram_size;
+
+	hiphybas = ram_size - PROLSIZE;
+
+	mem_init(&cmem, (char *) &_end, (char *)(PROLBASE+PROLSIZE));
+	makepages(&pmem, hiphybas);
+	init_mmu_swift((unsigned int)pmem.pctp - PROLBASE + hiphybas);
+
+	mem_init(&cio, (char *)(PROLBASE+PROLSIZE),
+	    (char *)(PROLBASE+PROLSIZE+IOMAPSIZE));
+
+	iommu_init(&ciommu, hiphybas);
+
+	/*
+	 */
+	init_idprom();
+	printk("NVRAM: id %s version %d\n", hw_idprom->id, hw_idprom->version);
+	if (!nographic)
+	    printk("Prom console: TCX %dx%d\n", q_width, q_height);
+	else
+	    printk("Prom console: serial\n");
+	sched_init();
+	le_probe();
+	init_net();
+	esp_probe();
+
+	bootdev = hw_idprom->boot_device;
+	printk("Boot device: %c\n", bootdev);
+	if (hw_idprom->kernel_size > 0) {
+	    printk("Kernel already loaded\n");
+	} else if (bootdev == 'n') {
+	    if (bootp() != 0) fatal();
+	    /*
+	     * boot_rec.bp_file cannot be used because system PROM
+	     * uses it to locate ourselves. If we load from boot_rec.bp_file,
+	     * we will loop reloading PROLL over and over again.
+	     * Thus we use traditional PROLL scheme HEXIPADDR.PROL (single L).
+	     */
+	    xtoa(myipaddr, fname, 8);
+	    fname[9] = '.';
+	    fname[10] = 'P';
+	    fname[11] = 'R';
+	    fname[12] = 'O';
+	    fname[13] = 'L';
+	    fname[14] = 0;
+	    
+	    if (load(boot_rec.bp_siaddr, fname) != 0) fatal();
+	} else if (bootdev == 'c') {
+	    if (esp_boot(0) != 0) fatal();
+	} else if (bootdev == 'd') {
+	    if (esp_boot(2) != 0) fatal();
+	}
+