translate.c

qemu虚拟机代码

	return;
    case 0x600e:		/* exts.b Rm,Rn */
	gen_op_movb_rN_T0(REG(B7_4));
	gen_op_movl_T0_rN(REG(B11_8));
	return;
    case 0x600f:		/* exts.w Rm,Rn */
	gen_op_movw_rN_T0(REG(B7_4));
	gen_op_movl_T0_rN(REG(B11_8));
	return;
    case 0x600c:		/* extu.b Rm,Rn */
	gen_op_movub_rN_T0(REG(B7_4));
	gen_op_movl_T0_rN(REG(B11_8));
	return;
    case 0x600d:		/* extu.w Rm,Rn */
	gen_op_movuw_rN_T0(REG(B7_4));
	gen_op_movl_T0_rN(REG(B11_8));
	return;
    case 0x000f:		/* mac.l @Rm+,@Rn- */
	gen_op_movl_rN_T0(REG(B11_8));
	gen_op_ldl_T0_T0(ctx);
	gen_op_movl_T0_T1();
	gen_op_movl_rN_T1(REG(B7_4));
	gen_op_ldl_T0_T0(ctx);
	gen_op_macl_T0_T1();
	gen_op_inc4_rN(REG(B7_4));
	gen_op_inc4_rN(REG(B11_8));
	return;
    case 0x400f:		/* mac.w @Rm+,@Rn+ */
	gen_op_movl_rN_T0(REG(B11_8));
	gen_op_ldl_T0_T0(ctx);
	gen_op_movl_T0_T1();
	gen_op_movl_rN_T1(REG(B7_4));
	gen_op_ldl_T0_T0(ctx);
	gen_op_macw_T0_T1();
	gen_op_inc2_rN(REG(B7_4));
	gen_op_inc2_rN(REG(B11_8));
	return;
    case 0x0007:		/* mul.l Rm,Rn */
	gen_op_movl_rN_T0(REG(B7_4));
	gen_op_movl_rN_T1(REG(B11_8));
	gen_op_mull_T0_T1();
	return;
    case 0x200f:		/* muls.w Rm,Rn */
	gen_op_movw_rN_T0(REG(B7_4));
	gen_op_movw_rN_T1(REG(B11_8));
	gen_op_mulsw_T0_T1();
	return;
    case 0x200e:		/* mulu.w Rm,Rn */
	gen_op_movuw_rN_T0(REG(B7_4));
	gen_op_movuw_rN_T1(REG(B11_8));
	gen_op_muluw_T0_T1();
	return;
    case 0x600b:		/* neg Rm,Rn */
	gen_op_movl_rN_T0(REG(B7_4));
	gen_op_neg_T0();
	gen_op_movl_T0_rN(REG(B11_8));
	return;
    case 0x600a:		/* negc Rm,Rn */
	gen_op_movl_rN_T0(REG(B7_4));
	gen_op_negc_T0();
	gen_op_movl_T0_rN(REG(B11_8));
	return;
    case 0x6007:		/* not Rm,Rn */
	gen_op_movl_rN_T0(REG(B7_4));
	gen_op_not_T0();
	gen_op_movl_T0_rN(REG(B11_8));
	return;
    case 0x200b:		/* or Rm,Rn */
	gen_op_movl_rN_T0(REG(B7_4));
	gen_op_or_T0_rN(REG(B11_8));
	return;
    case 0x400c:		/* shad Rm,Rn */
	gen_op_movl_rN_T0(REG(B7_4));
	gen_op_movl_rN_T1(REG(B11_8));
	gen_op_shad_T0_T1();
	gen_op_movl_T1_rN(REG(B11_8));
	return;
    case 0x400d:		/* shld Rm,Rn */
	gen_op_movl_rN_T0(REG(B7_4));
	gen_op_movl_rN_T1(REG(B11_8));
	gen_op_shld_T0_T1();
	gen_op_movl_T1_rN(REG(B11_8));
	return;
    case 0x3008:		/* sub Rm,Rn */
	gen_op_movl_rN_T0(REG(B7_4));
	gen_op_sub_T0_rN(REG(B11_8));
	return;
    case 0x300a:		/* subc Rm,Rn */
	gen_op_movl_rN_T0(REG(B7_4));
	gen_op_movl_rN_T1(REG(B11_8));
	gen_op_subc_T0_T1();
	gen_op_movl_T1_rN(REG(B11_8));
	return;
    case 0x300b:		/* subv Rm,Rn */
	gen_op_movl_rN_T0(REG(B7_4));
	gen_op_movl_rN_T1(REG(B11_8));
	gen_op_subv_T0_T1();
	gen_op_movl_T1_rN(REG(B11_8));
	return;
    case 0x2008:		/* tst Rm,Rn */
	gen_op_movl_rN_T0(REG(B7_4));
	gen_op_movl_rN_T1(REG(B11_8));
	gen_op_tst_T0_T1();
	return;
    case 0x200a:		/* xor Rm,Rn */
	gen_op_movl_rN_T0(REG(B7_4));
	gen_op_xor_T0_rN(REG(B11_8));
	return;
    }

    switch (ctx->opcode & 0xff00) {
    case 0xc900:		/* and #imm,R0 */
	gen_op_and_imm_rN(B7_0, REG(0));
	return;
    case 0xcd00:		/* and.b #imm,@(R0+GBR) */
	gen_op_movl_rN_T0(REG(0));
	gen_op_addl_GBR_T0();
	gen_op_movl_T0_T1();
	gen_op_ldb_T0_T0(ctx);
	gen_op_and_imm_T0(B7_0);
	gen_op_stb_T0_T1(ctx);
	return;
    case 0x8b00:		/* bf label */
	CHECK_NOT_DELAY_SLOT
	    gen_conditional_jump(ctx, ctx->pc + 2,
				 ctx->pc + 4 + B7_0s * 2);
	ctx->flags |= BRANCH_CONDITIONAL;
	return;
    case 0x8f00:		/* bf/s label */
	CHECK_NOT_DELAY_SLOT
	    gen_op_bf_s(ctx->delayed_pc = ctx->pc + 4 + B7_0s * 2);
	ctx->flags |= DELAY_SLOT_CONDITIONAL;
	return;
    case 0x8900:		/* bt label */
	CHECK_NOT_DELAY_SLOT
	    gen_conditional_jump(ctx, ctx->pc + 4 + B7_0s * 2,
				 ctx->pc + 2);
	ctx->flags |= BRANCH_CONDITIONAL;
	return;
    case 0x8d00:		/* bt/s label */
	CHECK_NOT_DELAY_SLOT
	    gen_op_bt_s(ctx->delayed_pc = ctx->pc + 4 + B7_0s * 2);
	ctx->flags |= DELAY_SLOT_CONDITIONAL;
	return;
    case 0x8800:		/* cmp/eq #imm,R0 */
	gen_op_movl_rN_T0(REG(0));
	gen_op_cmp_eq_imm_T0(B7_0s);
	return;
    case 0xc400:		/* mov.b @(disp,GBR),R0 */
	gen_op_stc_gbr_T0();
	gen_op_addl_imm_T0(B7_0);
	gen_op_ldb_T0_T0(ctx);
	gen_op_movl_T0_rN(REG(0));
	return;
    case 0xc500:		/* mov.w @(disp,GBR),R0 */
	gen_op_stc_gbr_T0();
	gen_op_addl_imm_T0(B7_0);
	gen_op_ldw_T0_T0(ctx);
	gen_op_movl_T0_rN(REG(0));
	return;
    case 0xc600:		/* mov.l @(disp,GBR),R0 */
	gen_op_stc_gbr_T0();
	gen_op_addl_imm_T0(B7_0);
	gen_op_ldl_T0_T0(ctx);
	gen_op_movl_T0_rN(REG(0));
	return;
    case 0xc000:		/* mov.b R0,@(disp,GBR) */
	gen_op_stc_gbr_T0();
	gen_op_addl_imm_T0(B7_0);
	gen_op_movl_T0_T1();
	gen_op_movl_rN_T0(REG(0));
	gen_op_stb_T0_T1(ctx);
	return;
    case 0xc100:		/* mov.w R0,@(disp,GBR) */
	gen_op_stc_gbr_T0();
	gen_op_addl_imm_T0(B7_0);
	gen_op_movl_T0_T1();
	gen_op_movl_rN_T0(REG(0));
	gen_op_stw_T0_T1(ctx);
	return;
    case 0xc200:		/* mov.l R0,@(disp,GBR) */
	gen_op_stc_gbr_T0();
	gen_op_addl_imm_T0(B7_0);
	gen_op_movl_T0_T1();
	gen_op_movl_rN_T0(REG(0));
	gen_op_stl_T0_T1(ctx);
	return;
    case 0x8000:		/* mov.b R0,@(disp,Rn) */
	gen_op_movl_rN_T0(REG(0));
	gen_op_movl_rN_T1(REG(B7_4));
	gen_op_addl_imm_T1(B3_0);
	gen_op_stb_T0_T1(ctx);
	return;
    case 0x8100:		/* mov.w R0,@(disp,Rn) */
	gen_op_movl_rN_T0(REG(0));
	gen_op_movl_rN_T1(REG(B7_4));
	gen_op_addl_imm_T1(B3_0 * 2);
	gen_op_stw_T0_T1(ctx);
	return;
    case 0x8400:		/* mov.b @(disp,Rn),R0 */
	gen_op_movl_rN_T0(REG(0));
	gen_op_movl_rN_T1(REG(B7_4));
	gen_op_addl_imm_T1(B3_0);
	gen_op_stb_T0_T1(ctx);
	return;
    case 0x8500:		/* mov.w @(disp,Rn),R0 */
	gen_op_movl_rN_T0(REG(B7_4));
	gen_op_addl_imm_T0(B3_0 * 2);
	gen_op_ldw_T0_T0(ctx);
	gen_op_movl_T0_rN(REG(0));
	return;
    case 0xc700:		/* mova @(disp,PC),R0 */
	gen_op_movl_imm_rN(((ctx->pc & 0xfffffffc) + 4 + B7_0 * 4) & ~3,
			   REG(0));
	return;
    case 0xcb00:		/* or #imm,R0 */
	gen_op_or_imm_rN(B7_0, REG(0));
	return;
    case 0xcf00:		/* or.b #imm,@(R0+GBR) */
	gen_op_movl_rN_T0(REG(0));
	gen_op_addl_GBR_T0();
	gen_op_movl_T0_T1();
	gen_op_ldb_T0_T0(ctx);
	gen_op_or_imm_T0(B7_0);
	gen_op_stb_T0_T1(ctx);
	return;
    case 0xc300:		/* trapa #imm */
	CHECK_NOT_DELAY_SLOT gen_op_movl_imm_PC(ctx->pc);
	gen_op_trapa(B7_0);
	ctx->flags |= BRANCH;
	return;
    case 0xc800:		/* tst #imm,R0 */
	gen_op_tst_imm_rN(B7_0, REG(0));
	return;
    case 0xcc00:		/* tst #imm,@(R0+GBR) */
	gen_op_movl_rN_T0(REG(0));
	gen_op_addl_GBR_T0();
	gen_op_ldb_T0_T0(ctx);
	gen_op_tst_imm_T0(B7_0);
	return;
    case 0xca00:		/* xor #imm,R0 */
	gen_op_xor_imm_rN(B7_0, REG(0));
	return;
    case 0xce00:		/* xor.b #imm,@(R0+GBR) */
	gen_op_movl_rN_T0(REG(0));
	gen_op_addl_GBR_T0();
	gen_op_movl_T0_T1();
	gen_op_ldb_T0_T0(ctx);
	gen_op_xor_imm_T0(B7_0);
	gen_op_stb_T0_T1(ctx);
	return;
    }

    switch (ctx->opcode & 0xf08f) {
    case 0x408e:		/* ldc Rm,Rn_BANK */
	gen_op_movl_rN_rN(REG(B11_8), ALTREG(B6_4));
	return;
    case 0x4087:		/* ldc.l @Rm+,Rn_BANK */
	gen_op_movl_rN_T0(REG(B11_8));
	gen_op_ldl_T0_T0(ctx);
	gen_op_movl_T0_rN(ALTREG(B6_4));
	gen_op_inc4_rN(REG(B11_8));
	return;
    case 0x0082:		/* stc Rm_BANK,Rn */
	gen_op_movl_rN_rN(ALTREG(B6_4), REG(B11_8));
	return;
    case 0x4083:		/* stc.l Rm_BANK,@-Rn */
	gen_op_dec4_rN(REG(B11_8));
	gen_op_movl_rN_T1(REG(B11_8));
	gen_op_movl_rN_T0(ALTREG(B6_4));
	gen_op_stl_T0_T1(ctx);
	return;
    }

    switch (ctx->opcode & 0xf0ff) {
    case 0x0023:		/* braf Rn */
	CHECK_NOT_DELAY_SLOT gen_op_movl_rN_T0(REG(B11_8));
	gen_op_braf_T0(ctx->pc + 4);
	ctx->flags |= DELAY_SLOT;
	ctx->delayed_pc = (uint32_t) - 1;
	return;
    case 0x0003:		/* bsrf Rn */
	CHECK_NOT_DELAY_SLOT gen_op_movl_rN_T0(REG(B11_8));
	gen_op_bsrf_T0(ctx->pc + 4);
	ctx->flags |= DELAY_SLOT;
	ctx->delayed_pc = (uint32_t) - 1;
	return;
    case 0x4015:		/* cmp/pl Rn */
	gen_op_movl_rN_T0(REG(B11_8));
	gen_op_cmp_pl_T0();
	return;
    case 0x4011:		/* cmp/pz Rn */
	gen_op_movl_rN_T0(REG(B11_8));
	gen_op_cmp_pz_T0();
	return;
    case 0x4010:		/* dt Rn */
	gen_op_dt_rN(REG(B11_8));
	return;
    case 0x402b:		/* jmp @Rn */
	CHECK_NOT_DELAY_SLOT gen_op_movl_rN_T0(REG(B11_8));
	gen_op_jmp_T0();
	ctx->flags |= DELAY_SLOT;
	ctx->delayed_pc = (uint32_t) - 1;
	return;
    case 0x400b:		/* jsr @Rn */
	CHECK_NOT_DELAY_SLOT gen_op_movl_rN_T0(REG(B11_8));
	gen_op_jsr_T0(ctx->pc + 4);
	ctx->flags |= DELAY_SLOT;
	ctx->delayed_pc = (uint32_t) - 1;
	return;
#define LDST(reg,ldnum,ldpnum,ldop,stnum,stpnum,stop,extrald)	\
  case ldnum:							\
    gen_op_movl_rN_T0 (REG(B11_8));				\
    gen_op_##ldop##_T0_##reg ();				\
    extrald							\
    return;							\
  case ldpnum:							\
    gen_op_movl_rN_T0 (REG(B11_8));				\
    gen_op_ldl_T0_T0 (ctx);					\
    gen_op_inc4_rN (REG(B11_8));				\
    gen_op_##ldop##_T0_##reg ();				\
    extrald							\
    return;							\
  case stnum:							\
    gen_op_##stop##_##reg##_T0 ();					\
    gen_op_movl_T0_rN (REG(B11_8));				\
    return;							\
  case stpnum:							\
    gen_op_##stop##_##reg##_T0 ();				\
    gen_op_dec4_rN (REG(B11_8));				\
    gen_op_movl_rN_T1 (REG(B11_8));				\
    gen_op_stl_T0_T1 (ctx);					\
    return;
	LDST(sr, 0x400e, 0x4007, ldc, 0x0002, 0x4003, stc, ctx->flags |=
	     MODE_CHANGE;
	    )
	    LDST(gbr, 0x401e, 0x4017, ldc, 0x0012, 0x4013, stc,)
	    LDST(vbr, 0x402e, 0x4027, ldc, 0x0022, 0x4023, stc,)
	    LDST(ssr, 0x403e, 0x4037, ldc, 0x0032, 0x4033, stc,)
	    LDST(spc, 0x404e, 0x4047, ldc, 0x0042, 0x4043, stc,)
	    LDST(dbr, 0x40fa, 0x40f6, ldc, 0x00fa, 0x40f2, stc,)
	    LDST(mach, 0x400a, 0x4006, lds, 0x000a, 0x4002, sts,)
	    LDST(macl, 0x401a, 0x4016, lds, 0x001a, 0x4012, sts,)
	    LDST(pr, 0x402a, 0x4026, lds, 0x002a, 0x4022, sts,)
    case 0x00c3:		/* movca.l R0,@Rm */
	gen_op_movl_rN_T0(REG(0));
	gen_op_movl_rN_T1(REG(B11_8));
	gen_op_stl_T0_T1(ctx);
	return;
    case 0x0029:		/* movt Rn */
	gen_op_movt_rN(REG(B11_8));
	return;
    case 0x0093:		/* ocbi @Rn */
	gen_op_movl_rN_T0(REG(B11_8));
	gen_op_ldl_T0_T0(ctx);
	return;
    case 0x00a2:		/* ocbp @Rn */
	gen_op_movl_rN_T0(REG(B11_8));
	gen_op_ldl_T0_T0(ctx);
	return;
    case 0x00b3:		/* ocbwb @Rn */
	gen_op_movl_rN_T0(REG(B11_8));
	gen_op_ldl_T0_T0(ctx);
	return;
    case 0x0083:		/* pref @Rn */
	return;
    case 0x4024:		/* rotcl Rn */
	gen_op_rotcl_Rn(REG(B11_8));
	return;
    case 0x4025:		/* rotcr Rn */
	gen_op_rotcr_Rn(REG(B11_8));
	return;
    case 0x4004:		/* rotl Rn */
	gen_op_rotl_Rn(REG(B11_8));
	return;
    case 0x4005:		/* rotr Rn */
	gen_op_rotr_Rn(REG(B11_8));
	return;
    case 0x4000:		/* shll Rn */
    case 0x4020:		/* shal Rn */
	gen_op_shal_Rn(REG(B11_8));
	return;
    case 0x4021:		/* shar Rn */
	gen_op_shar_Rn(REG(B11_8));
	return;
    case 0x4001:		/* shlr Rn */
	gen_op_shlr_Rn(REG(B11_8));
	return;
    case 0x4008:		/* shll2 Rn */
	gen_op_shll2_Rn(REG(B11_8));
	return;
    case 0x4018:		/* shll8 Rn */
	gen_op_shll8_Rn(REG(B11_8));
	return;
    case 0x4028:		/* shll16 Rn */
	gen_op_shll16_Rn(REG(B11_8));
	return;
    case 0x4009:		/* shlr2 Rn */
	gen_op_shlr2_Rn(REG(B11_8));
	return;
    case 0x4019:		/* shlr8 Rn */
	gen_op_shlr8_Rn(REG(B11_8));
	return;
    case 0x4029:		/* shlr16 Rn */
	gen_op_shlr16_Rn(REG(B11_8));
	return;
    case 0x401b:		/* tas.b @Rn */
	gen_op_tasb_rN(REG(B11_8));
	return;
    }

    fprintf(stderr, "unknown instruction 0x%04x at pc 0x%08x\n",
	    ctx->opcode, ctx->pc);
    gen_op_raise_illegal_instruction();
    ctx->flags |= BRANCH_EXCEPTION;
}

int gen_intermediate_code_internal(CPUState * env, TranslationBlock * tb,
				   int search_pc)
{
    DisasContext ctx;
    target_ulong pc_start;
    static uint16_t *gen_opc_end;
    uint32_t old_flags;
    int i;

    pc_start = tb->pc;
    gen_opc_ptr = gen_opc_buf;
    gen_opc_end = gen_opc_buf + OPC_MAX_SIZE;
    gen_opparam_ptr = gen_opparam_buf;
    ctx.pc = pc_start;
    ctx.flags = env->flags;
    old_flags = 0;
    ctx.sr = env->sr;
    ctx.memidx = (env->sr & SR_MD) ? 1 : 0;
    ctx.delayed_pc = env->delayed_pc;
    ctx.tb = tb;
    ctx.singlestep_enabled = env->singlestep_enabled;
    nb_gen_labels = 0;

#ifdef DEBUG_DISAS
    if (loglevel & CPU_LOG_TB_CPU) {
	fprintf(logfile,
		"------------------------------------------------\n");
	cpu_dump_state(env, logfile, fprintf, 0);
    }
#endif

    while ((old_flags & (DELAY_SLOT | DELAY_SLOT_CONDITIONAL)) == 0 &&
	   (ctx.flags & (BRANCH | BRANCH_CONDITIONAL | MODE_CHANGE |
			 BRANCH_EXCEPTION)) == 0 &&
	   gen_opc_ptr < gen_opc_end && ctx.sr == env->sr) {
	old_flags = ctx.flags;
	if (env->nb_breakpoints > 0) {
	    for (i = 0; i < env->nb_breakpoints; i++) {
		if (ctx.pc == env->breakpoints[i]) {
		    /* We have hit a breakpoint - make sure PC is up-to-date */
		    gen_op_movl_imm_PC(ctx.pc);
		    gen_op_debug();
		    ctx.flags |= BRANCH_EXCEPTION;
		    break;
		}
	    }
	}
#if 0
	fprintf(stderr, "Loading opcode at address 0x%08x\n", ctx.pc);
	fflush(stderr);
#endif
	ctx.opcode = lduw_code(ctx.pc);
	decode_opc(&ctx);
	ctx.pc += 2;
	if ((ctx.pc & (TARGET_PAGE_SIZE - 1)) == 0)
	    break;
	if (env->singlestep_enabled)
	    break;
#ifdef SH4_SINGLE_STEP
	break;
#endif
    }

    switch (old_flags & (DELAY_SLOT_CONDITIONAL | DELAY_SLOT)) {
    case DELAY_SLOT_CONDITIONAL:
	gen_op_clr_delay_slot_conditional();
	gen_delayed_conditional_jump(&ctx);
	break;
    case DELAY_SLOT:
	gen_op_clr_delay_slot();
	gen_jump(&ctx);
	break;
    case 0:
	if (ctx.flags & BRANCH_EXCEPTION) {
	    gen_jump_exception(&ctx);
	} else if ((ctx.flags & (BRANCH | BRANCH_CONDITIONAL)) == 0) {
	    gen_goto_tb(&ctx, 0, ctx.pc);
	}
	break;
    default:
	/* Both cannot be set at the same time */
	assert(0);
    }

    if (env->singlestep_enabled) {
	gen_op_debug();
    }
    *gen_opc_ptr = INDEX_op_end;
    tb->size = ctx.pc - pc_start;

#ifdef DEBUG_DISAS
#ifdef SH4_DEBUG_DISAS
    if (loglevel & CPU_LOG_TB_IN_ASM)
	fprintf(logfile, "\n");
#endif
    if (loglevel & CPU_LOG_TB_IN_ASM) {
	fprintf(logfile, "IN:\n");	/* , lookup_symbol(pc_start)); */
	target_disas(logfile, pc_start, ctx.pc - pc_start, 0);
	fprintf(logfile, "\n");
    }
    if (loglevel & CPU_LOG_TB_OP) {
	fprintf(logfile, "OP:\n");
	dump_ops(gen_opc_buf, gen_opparam_buf);
	fprintf(logfile, "\n");
    }
#endif
    return 0;
}

int gen_intermediate_code(CPUState * env, struct TranslationBlock *tb)
{
    return gen_intermediate_code_internal(env, tb, 0);
}

int gen_intermediate_code_pc(CPUState * env, struct TranslationBlock *tb)
{
    assert(0);
    return gen_intermediate_code_internal(env, tb, 1);
}