translate.c

qemu虚拟机代码

			break;
		    case 0x042: /* V9 fmovdcc %fcc1 */
			cond = GET_FIELD_SP(insn, 14, 17);
                	gen_op_load_fpr_DT0(rd);
                	gen_op_load_fpr_DT1(rs2);
			flush_T2(dc);
			gen_fcond[1][cond]();
			gen_op_fmovd_cc();
			gen_op_store_DT0_fpr(rd);
			break;
		    case 0x043: /* V9 fmovqcc %fcc1 */
		        goto nfpu_insn;
		    case 0x081: /* V9 fmovscc %fcc2 */
			cond = GET_FIELD_SP(insn, 14, 17);
                	gen_op_load_fpr_FT0(rd);
                	gen_op_load_fpr_FT1(rs2);
			flush_T2(dc);
			gen_fcond[2][cond]();
			gen_op_fmovs_cc();
			gen_op_store_FT0_fpr(rd);
			break;
		    case 0x082: /* V9 fmovdcc %fcc2 */
			cond = GET_FIELD_SP(insn, 14, 17);
                	gen_op_load_fpr_DT0(rd);
                	gen_op_load_fpr_DT1(rs2);
			flush_T2(dc);
			gen_fcond[2][cond]();
			gen_op_fmovd_cc();
			gen_op_store_DT0_fpr(rd);
			break;
		    case 0x083: /* V9 fmovqcc %fcc2 */
		        goto nfpu_insn;
		    case 0x0c1: /* V9 fmovscc %fcc3 */
			cond = GET_FIELD_SP(insn, 14, 17);
                	gen_op_load_fpr_FT0(rd);
                	gen_op_load_fpr_FT1(rs2);
			flush_T2(dc);
			gen_fcond[3][cond]();
			gen_op_fmovs_cc();
			gen_op_store_FT0_fpr(rd);
			break;
		    case 0x0c2: /* V9 fmovdcc %fcc3 */
			cond = GET_FIELD_SP(insn, 14, 17);
                	gen_op_load_fpr_DT0(rd);
                	gen_op_load_fpr_DT1(rs2);
			flush_T2(dc);
			gen_fcond[3][cond]();
			gen_op_fmovd_cc();
			gen_op_store_DT0_fpr(rd);
			break;
		    case 0x0c3: /* V9 fmovqcc %fcc3 */
		        goto nfpu_insn;
		    case 0x101: /* V9 fmovscc %icc */
			cond = GET_FIELD_SP(insn, 14, 17);
                	gen_op_load_fpr_FT0(rd);
                	gen_op_load_fpr_FT1(rs2);
			flush_T2(dc);
			gen_cond[0][cond]();
			gen_op_fmovs_cc();
			gen_op_store_FT0_fpr(rd);
			break;
		    case 0x102: /* V9 fmovdcc %icc */
			cond = GET_FIELD_SP(insn, 14, 17);
                	gen_op_load_fpr_DT0(rd);
                	gen_op_load_fpr_DT1(rs2);
			flush_T2(dc);
			gen_cond[0][cond]();
			gen_op_fmovd_cc();
			gen_op_store_DT0_fpr(rd);
			break;
		    case 0x103: /* V9 fmovqcc %icc */
		        goto nfpu_insn;
		    case 0x181: /* V9 fmovscc %xcc */
			cond = GET_FIELD_SP(insn, 14, 17);
                	gen_op_load_fpr_FT0(rd);
                	gen_op_load_fpr_FT1(rs2);
			flush_T2(dc);
			gen_cond[1][cond]();
			gen_op_fmovs_cc();
			gen_op_store_FT0_fpr(rd);
			break;
		    case 0x182: /* V9 fmovdcc %xcc */
			cond = GET_FIELD_SP(insn, 14, 17);
                	gen_op_load_fpr_DT0(rd);
                	gen_op_load_fpr_DT1(rs2);
			flush_T2(dc);
			gen_cond[1][cond]();
			gen_op_fmovd_cc();
			gen_op_store_DT0_fpr(rd);
			break;
		    case 0x183: /* V9 fmovqcc %xcc */
		        goto nfpu_insn;
#endif
		    case 0x51: /* V9 %fcc */
                	gen_op_load_fpr_FT0(rs1);
                	gen_op_load_fpr_FT1(rs2);
#ifdef TARGET_SPARC64
			gen_fcmps[rd & 3]();
#else
			gen_op_fcmps();
#endif
			break;
		    case 0x52: /* V9 %fcc */
                	gen_op_load_fpr_DT0(DFPREG(rs1));
                	gen_op_load_fpr_DT1(DFPREG(rs2));
#ifdef TARGET_SPARC64
			gen_fcmpd[rd & 3]();
#else
			gen_op_fcmpd();
#endif
			break;
		    case 0x53: /* fcmpq */
		        goto nfpu_insn;
		    case 0x55: /* fcmpes, V9 %fcc */
                	gen_op_load_fpr_FT0(rs1);
                	gen_op_load_fpr_FT1(rs2);
#ifdef TARGET_SPARC64
			gen_fcmps[rd & 3]();
#else
			gen_op_fcmps(); /* XXX should trap if qNaN or sNaN  */
#endif
			break;
		    case 0x56: /* fcmped, V9 %fcc */
                	gen_op_load_fpr_DT0(DFPREG(rs1));
                	gen_op_load_fpr_DT1(DFPREG(rs2));
#ifdef TARGET_SPARC64
			gen_fcmpd[rd & 3]();
#else
			gen_op_fcmpd(); /* XXX should trap if qNaN or sNaN  */
#endif
			break;
		    case 0x57: /* fcmpeq */
		        goto nfpu_insn;
		    default:
                	goto illegal_insn;
		}
#if defined(OPTIM)
	    } else if (xop == 0x2) {
		// clr/mov shortcut

                rs1 = GET_FIELD(insn, 13, 17);
		if (rs1 == 0) {
		    // or %g0, x, y -> mov T1, x; mov y, T1
		    if (IS_IMM) {	/* immediate */
			rs2 = GET_FIELDs(insn, 19, 31);
			gen_movl_simm_T1(rs2);
		    } else {		/* register */
			rs2 = GET_FIELD(insn, 27, 31);
			gen_movl_reg_T1(rs2);
		    }
		    gen_movl_T1_reg(rd);
		} else {
		    gen_movl_reg_T0(rs1);
		    if (IS_IMM) {	/* immediate */
			// or x, #0, y -> mov T1, x; mov y, T1
			rs2 = GET_FIELDs(insn, 19, 31);
			if (rs2 != 0) {
			    gen_movl_simm_T1(rs2);
			    gen_op_or_T1_T0();
			}
		    } else {		/* register */
			// or x, %g0, y -> mov T1, x; mov y, T1
			rs2 = GET_FIELD(insn, 27, 31);
			if (rs2 != 0) {
			    gen_movl_reg_T1(rs2);
			    gen_op_or_T1_T0();
			}
		    }
		    gen_movl_T0_reg(rd);
		}
#endif
#ifdef TARGET_SPARC64
	    } else if (xop == 0x25) { /* sll, V9 sllx ( == sll) */
                rs1 = GET_FIELD(insn, 13, 17);
		gen_movl_reg_T0(rs1);
		if (IS_IMM) {	/* immediate */
                    rs2 = GET_FIELDs(insn, 20, 31);
                    gen_movl_simm_T1(rs2);
                } else {		/* register */
                    rs2 = GET_FIELD(insn, 27, 31);
                    gen_movl_reg_T1(rs2);
                }
		gen_op_sll();
		gen_movl_T0_reg(rd);
	    } else if (xop == 0x26) { /* srl, V9 srlx */
                rs1 = GET_FIELD(insn, 13, 17);
		gen_movl_reg_T0(rs1);
		if (IS_IMM) {	/* immediate */
                    rs2 = GET_FIELDs(insn, 20, 31);
                    gen_movl_simm_T1(rs2);
                } else {		/* register */
                    rs2 = GET_FIELD(insn, 27, 31);
                    gen_movl_reg_T1(rs2);
                }
		if (insn & (1 << 12))
		    gen_op_srlx();
		else
		    gen_op_srl();
		gen_movl_T0_reg(rd);
	    } else if (xop == 0x27) { /* sra, V9 srax */
                rs1 = GET_FIELD(insn, 13, 17);
		gen_movl_reg_T0(rs1);
		if (IS_IMM) {	/* immediate */
                    rs2 = GET_FIELDs(insn, 20, 31);
                    gen_movl_simm_T1(rs2);
                } else {		/* register */
                    rs2 = GET_FIELD(insn, 27, 31);
                    gen_movl_reg_T1(rs2);
                }
		if (insn & (1 << 12))
		    gen_op_srax();
		else
		    gen_op_sra();
		gen_movl_T0_reg(rd);
#endif
	    } else if (xop < 0x38) {
                rs1 = GET_FIELD(insn, 13, 17);
		gen_movl_reg_T0(rs1);
		if (IS_IMM) {	/* immediate */
                    rs2 = GET_FIELDs(insn, 19, 31);
                    gen_movl_simm_T1(rs2);
                } else {		/* register */
                    rs2 = GET_FIELD(insn, 27, 31);
                    gen_movl_reg_T1(rs2);
                }
                if (xop < 0x20) {
                    switch (xop & ~0x10) {
                    case 0x0:
                        if (xop & 0x10)
                            gen_op_add_T1_T0_cc();
                        else
                            gen_op_add_T1_T0();
                        break;
                    case 0x1:
                        gen_op_and_T1_T0();
                        if (xop & 0x10)
                            gen_op_logic_T0_cc();
                        break;
                    case 0x2:
			gen_op_or_T1_T0();
			if (xop & 0x10)
			    gen_op_logic_T0_cc();
			break;
                    case 0x3:
                        gen_op_xor_T1_T0();
                        if (xop & 0x10)
                            gen_op_logic_T0_cc();
                        break;
                    case 0x4:
                        if (xop & 0x10)
                            gen_op_sub_T1_T0_cc();
                        else
                            gen_op_sub_T1_T0();
                        break;
                    case 0x5:
                        gen_op_andn_T1_T0();
                        if (xop & 0x10)
                            gen_op_logic_T0_cc();
                        break;
                    case 0x6:
                        gen_op_orn_T1_T0();
                        if (xop & 0x10)
                            gen_op_logic_T0_cc();
                        break;
                    case 0x7:
                        gen_op_xnor_T1_T0();
                        if (xop & 0x10)
                            gen_op_logic_T0_cc();
                        break;
                    case 0x8:
                        if (xop & 0x10)
                            gen_op_addx_T1_T0_cc();
                        else
                            gen_op_addx_T1_T0();
                        break;
                    case 0xa:
                        gen_op_umul_T1_T0();
                        if (xop & 0x10)
                            gen_op_logic_T0_cc();
                        break;
                    case 0xb:
                        gen_op_smul_T1_T0();
                        if (xop & 0x10)
                            gen_op_logic_T0_cc();
                        break;
                    case 0xc:
                        if (xop & 0x10)
                            gen_op_subx_T1_T0_cc();
                        else
                            gen_op_subx_T1_T0();
                        break;
                    case 0xe:
                        gen_op_udiv_T1_T0();
                        if (xop & 0x10)
                            gen_op_div_cc();
                        break;
                    case 0xf:
                        gen_op_sdiv_T1_T0();
                        if (xop & 0x10)
                            gen_op_div_cc();
                        break;
                    default:
                        goto illegal_insn;
                    }
		    gen_movl_T0_reg(rd);
                } else {
                    switch (xop) {
#ifdef TARGET_SPARC64
		    case 0x9: /* V9 mulx */
                        gen_op_mulx_T1_T0();
			gen_movl_T0_reg(rd);
                        break;
		    case 0xd: /* V9 udivx */
                        gen_op_udivx_T1_T0();
			gen_movl_T0_reg(rd);
                        break;
#endif
		    case 0x20: /* taddcc */
		    case 0x21: /* tsubcc */
		    case 0x22: /* taddcctv */
		    case 0x23: /* tsubcctv */
			goto illegal_insn;
                    case 0x24: /* mulscc */
                        gen_op_mulscc_T1_T0();
                        gen_movl_T0_reg(rd);
                        break;
#ifndef TARGET_SPARC64
                    case 0x25:	/* sll */
			gen_op_sll();
                        gen_movl_T0_reg(rd);
                        break;
                    case 0x26:  /* srl */
			gen_op_srl();
                        gen_movl_T0_reg(rd);
                        break;
                    case 0x27:  /* sra */
			gen_op_sra();
                        gen_movl_T0_reg(rd);
                        break;
#endif
                    case 0x30:
                        {
                            switch(rd) {
                            case 0: /* wry */
				gen_op_xor_T1_T0();
				gen_op_movtl_env_T0(offsetof(CPUSPARCState, y));
                                break;
#ifdef TARGET_SPARC64
			    case 0x2: /* V9 wrccr */
                                gen_op_wrccr();
				break;
			    case 0x3: /* V9 wrasi */
				gen_op_movl_env_T0(offsetof(CPUSPARCState, asi));
				break;
			    case 0x6: /* V9 wrfprs */
				gen_op_movl_env_T0(offsetof(CPUSPARCState, fprs));
				break;
			    case 0xf: /* V9 sir, nop if user */
#if !defined(CONFIG_USER_ONLY)
				if (supervisor(dc))
				    gen_op_sir();
#endif
				break;
			    case 0x17: /* Tick compare */
#if !defined(CONFIG_USER_ONLY)
				if (!supervisor(dc))
				    goto illegal_insn;
#endif
				gen_op_movtl_env_T0(offsetof(CPUSPARCState, tick_cmpr));
				break;
			    case 0x18: /* System tick */
#if !defined(CONFIG_USER_ONLY)
				if (!supervisor(dc))
				    goto illegal_insn;
#endif
				gen_op_movtl_env_T0(offsetof(CPUSPARCState, stick_cmpr));
				break;
			    case 0x19: /* System tick compare */
#if !defined(CONFIG_USER_ONLY)
				if (!supervisor(dc))
				    goto illegal_insn;
#endif
				gen_op_movtl_env_T0(offsetof(CPUSPARCState, stick_cmpr));
				break;

			    case 0x10: /* Performance Control */
			    case 0x11: /* Performance Instrumentation Counter */
			    case 0x12: /* Dispatch Control */
			    case 0x13: /* Graphics Status */
			    case 0x14: /* Softint set */
			    case 0x15: /* Softint clear */
			    case 0x16: /* Softint write */
#endif
                            default:
                                goto illegal_insn;
                            }
                        }
                        break;
#if !defined(CONFIG_USER_ONLY)
                    case 0x31: /* wrpsr, V9 saved, restored */
                        {
			    if (!supervisor(dc))
				goto priv_insn;
#ifdef TARGET_SPARC64
			    switch (rd) {
			    case 0:
				gen_op_saved();
				break;
			    case 1:
				gen_op_restored();
				break;
			    default:
                                goto illegal_insn;
                            }
#else
                            gen_op_xor_T1_T0();
                            gen_op_wrpsr();
                            save_state(dc);
                            gen_op_next_insn();
			    gen_op_movl_T0_0();
			    gen_op_exit_tb();
			    dc->is_br = 1;
#endif
                        }
                        break;
                    case 0x32: /* wrwim, V9 wrpr */
                        {
			    if (!supervisor(dc))
				goto priv_insn;
                            gen_op_xor_T1_T0();
#ifdef TARGET_SPARC64
			    switch (rd) {
			    case 0: // tpc
				gen_op_wrtpc();
				break;
			    case 1: // tnpc
				gen_op_wrtnpc();
				break;
			    case 2: // tstate
				gen_op_wrtstate();
				break;
			    case 3: // tt
				gen_op_wrtt();
				break;
			    case 4: // tick
				gen_op_wrtick();
				break;
			    case 5: // tba
				gen_op_movtl_env_T0(offsetof(CPUSPARCState, tbr));
				break;
			    case 6: // pstate
				gen_op_wrpstate();
				break;
			    case 7: // tl
				gen_op_movl_env_T0(offsetof(CPUSPARCState, tl));
				break;
			    case 8: // pil
				gen_op_movl_env_T0(offsetof(CPUSPARCState, psrpil));
				break;
			    case 9: // cwp
				gen_op_wrcwp();
				break;
			    case 10: // cansave
				gen_op_movl_env_T0(offsetof(CPUSPARCState, cansave));
				break;
			    case 11: // canrestore
				gen_op_movl_env_T0(offsetof(CPUSPARCState, canrestore));
				break;
			    case 12: // cleanwin
				gen_op_movl_env_T0(offsetof(CPUSPARCState, cleanwin));
				break;
			    case 13: // otherwin
				gen_op_movl_env_T0(offsetof(CPUSPARCState, otherwin));
				break;
			    case 14: // wstate
				gen_op_movl_env_T0(offsetof(CPUSPARCState, wstate));
				break;
			    default:
				goto illegal_insn;
			    }
#else
			    gen_op_movl_env_T0(offsetof(CPUSPARCState, wim));
#endif
                        }
                        break;
#ifndef TARGET_SPARC64
                    case 0x33: /* wrtbr, V9 unimp */
                        {
			    if (!supervisor(dc))
				goto priv_insn;
                            gen_op_xor_T1_T0();
			    gen_op_movtl_env_T0(offsetof(CPUSPARCState, tbr));
                        }
                        break;
#endif
#endif