test-i386.c

qemu虚拟机代码

    printf("esp_val=" FMTLX "\n", esp_val - (long)stack_end);\
    printf("ebp_val=" FMTLX "\n", ebp_val - (long)stack_end);\
    for(ptr = (stack_type *)esp_val; ptr < stack_end; ptr++)\
        printf(FMTLX "\n", (long)ptr[0]);\
}

static void test_enter(void)
{
#if defined(__x86_64__)
    TEST_ENTER("q", uint64_t, 0);
    TEST_ENTER("q", uint64_t, 1);
    TEST_ENTER("q", uint64_t, 2);
    TEST_ENTER("q", uint64_t, 31);
#else
    TEST_ENTER("l", uint32_t, 0);
    TEST_ENTER("l", uint32_t, 1);
    TEST_ENTER("l", uint32_t, 2);
    TEST_ENTER("l", uint32_t, 31);
#endif

    TEST_ENTER("w", uint16_t, 0);
    TEST_ENTER("w", uint16_t, 1);
    TEST_ENTER("w", uint16_t, 2);
    TEST_ENTER("w", uint16_t, 31);
}

#ifdef TEST_SSE

typedef int __m64 __attribute__ ((__mode__ (__V2SI__)));
typedef int __m128 __attribute__ ((__mode__(__V4SF__)));

typedef union {
    double d[2];
    float s[4];
    uint32_t l[4];
    uint64_t q[2];
    __m128 dq;
} XMMReg;

static uint64_t __attribute__((aligned(16))) test_values[4][2] = {
    { 0x456723c698694873, 0xdc515cff944a58ec },
    { 0x1f297ccd58bad7ab, 0x41f21efba9e3e146 },
    { 0x007c62c2085427f8, 0x231be9e8cde7438d },
    { 0x0f76255a085427f8, 0xc233e9e8c4c9439a },
};

#define SSE_OP(op)\
{\
    asm volatile (#op " %2, %0" : "=x" (r.dq) : "0" (a.dq), "x" (b.dq));\
    printf("%-9s: a=" FMT64X "" FMT64X " b=" FMT64X "" FMT64X " r=" FMT64X "" FMT64X "\n",\
           #op,\
           a.q[1], a.q[0],\
           b.q[1], b.q[0],\
           r.q[1], r.q[0]);\
}

#define SSE_OP2(op)\
{\
    int i;\
    for(i=0;i<2;i++) {\
    a.q[0] = test_values[2*i][0];\
    a.q[1] = test_values[2*i][1];\
    b.q[0] = test_values[2*i+1][0];\
    b.q[1] = test_values[2*i+1][1];\
    SSE_OP(op);\
    }\
}

#define MMX_OP2(op)\
{\
    int i;\
    for(i=0;i<2;i++) {\
    a.q[0] = test_values[2*i][0];\
    b.q[0] = test_values[2*i+1][0];\
    asm volatile (#op " %2, %0" : "=y" (r.q[0]) : "0" (a.q[0]), "y" (b.q[0]));\
    printf("%-9s: a=" FMT64X " b=" FMT64X " r=" FMT64X "\n",\
           #op,\
           a.q[0],\
           b.q[0],\
           r.q[0]);\
    }\
    SSE_OP2(op);\
}

#define SHUF_OP(op, ib)\
{\
    a.q[0] = test_values[0][0];\
    a.q[1] = test_values[0][1];\
    b.q[0] = test_values[1][0];\
    b.q[1] = test_values[1][1];\
    asm volatile (#op " $" #ib ", %2, %0" : "=x" (r.dq) : "0" (a.dq), "x" (b.dq));\
    printf("%-9s: a=" FMT64X "" FMT64X " b=" FMT64X "" FMT64X " ib=%02x r=" FMT64X "" FMT64X "\n",\
           #op,\
           a.q[1], a.q[0],\
           b.q[1], b.q[0],\
           ib,\
           r.q[1], r.q[0]);\
}

#define PSHUF_OP(op, ib)\
{\
    int i;\
    for(i=0;i<2;i++) {\
    a.q[0] = test_values[2*i][0];\
    a.q[1] = test_values[2*i][1];\
    asm volatile (#op " $" #ib ", %1, %0" : "=x" (r.dq) : "x" (a.dq));\
    printf("%-9s: a=" FMT64X "" FMT64X " ib=%02x r=" FMT64X "" FMT64X "\n",\
           #op,\
           a.q[1], a.q[0],\
           ib,\
           r.q[1], r.q[0]);\
    }\
}

#define SHIFT_IM(op, ib)\
{\
    int i;\
    for(i=0;i<2;i++) {\
    a.q[0] = test_values[2*i][0];\
    a.q[1] = test_values[2*i][1];\
    asm volatile (#op " $" #ib ", %0" : "=x" (r.dq) : "0" (a.dq));\
    printf("%-9s: a=" FMT64X "" FMT64X " ib=%02x r=" FMT64X "" FMT64X "\n",\
           #op,\
           a.q[1], a.q[0],\
           ib,\
           r.q[1], r.q[0]);\
    }\
}

#define SHIFT_OP(op, ib)\
{\
    int i;\
    SHIFT_IM(op, ib);\
    for(i=0;i<2;i++) {\
    a.q[0] = test_values[2*i][0];\
    a.q[1] = test_values[2*i][1];\
    b.q[0] = ib;\
    b.q[1] = 0;\
    asm volatile (#op " %2, %0" : "=x" (r.dq) : "0" (a.dq), "x" (b.dq));\
    printf("%-9s: a=" FMT64X "" FMT64X " b=" FMT64X "" FMT64X " r=" FMT64X "" FMT64X "\n",\
           #op,\
           a.q[1], a.q[0],\
           b.q[1], b.q[0],\
           r.q[1], r.q[0]);\
    }\
}

#define MOVMSK(op)\
{\
    int i, reg;\
    for(i=0;i<2;i++) {\
    a.q[0] = test_values[2*i][0];\
    a.q[1] = test_values[2*i][1];\
    asm volatile (#op " %1, %0" : "=r" (reg) : "x" (a.dq));\
    printf("%-9s: a=" FMT64X "" FMT64X " r=%08x\n",\
           #op,\
           a.q[1], a.q[0],\
           reg);\
    }\
}

#define SSE_OPS(a) \
SSE_OP(a ## ps);\
SSE_OP(a ## ss);

#define SSE_OPD(a) \
SSE_OP(a ## pd);\
SSE_OP(a ## sd);

#define SSE_COMI(op, field)\
{\
    unsigned int eflags;\
    XMMReg a, b;\
    a.field[0] = a1;\
    b.field[0] = b1;\
    asm volatile (#op " %2, %1\n"\
        "pushf\n"\
        "pop %0\n"\
        : "=m" (eflags)\
        : "x" (a.dq), "x" (b.dq));\
    printf("%-9s: a=%f b=%f cc=%04x\n",\
           #op, a1, b1,\
           eflags & (CC_C | CC_P | CC_Z | CC_S | CC_O | CC_A));\
}

void test_sse_comi(double a1, double b1)
{
    SSE_COMI(ucomiss, s);
    SSE_COMI(ucomisd, d);
    SSE_COMI(comiss, s);
    SSE_COMI(comisd, d);
}

#define CVT_OP_XMM(op)\
{\
    asm volatile (#op " %1, %0" : "=x" (r.dq) : "x" (a.dq));\
    printf("%-9s: a=" FMT64X "" FMT64X " r=" FMT64X "" FMT64X "\n",\
           #op,\
           a.q[1], a.q[0],\
           r.q[1], r.q[0]);\
}

#define CVT_OP_XMM2MMX(op)\
{\
    asm volatile (#op " %1, %0" : "=y" (r.q[0]) : "x" (a.dq));\
    printf("%-9s: a=" FMT64X "" FMT64X " r=" FMT64X "\n",\
           #op,\
           a.q[1], a.q[0],\
           r.q[0]);\
}

#define CVT_OP_MMX2XMM(op)\
{\
    asm volatile (#op " %1, %0" : "=x" (r.dq) : "y" (a.q[0]));\
    printf("%-9s: a=" FMT64X " r=" FMT64X "" FMT64X "\n",\
           #op,\
           a.q[0],\
           r.q[1], r.q[0]);\
}

#define CVT_OP_REG2XMM(op)\
{\
    asm volatile (#op " %1, %0" : "=x" (r.dq) : "r" (a.l[0]));\
    printf("%-9s: a=%08x r=" FMT64X "" FMT64X "\n",\
           #op,\
           a.l[0],\
           r.q[1], r.q[0]);\
}

#define CVT_OP_XMM2REG(op)\
{\
    asm volatile (#op " %1, %0" : "=r" (r.l[0]) : "x" (a.dq));\
    printf("%-9s: a=" FMT64X "" FMT64X " r=%08x\n",\
           #op,\
           a.q[1], a.q[0],\
           r.l[0]);\
}

struct fpxstate {
    uint16_t fpuc;
    uint16_t fpus;
    uint16_t fptag;
    uint16_t fop;
    uint32_t fpuip;
    uint16_t cs_sel;
    uint16_t dummy0;
    uint32_t fpudp;
    uint16_t ds_sel;
    uint16_t dummy1;
    uint32_t mxcsr;
    uint32_t mxcsr_mask;
    uint8_t fpregs1[8 * 16];
    uint8_t xmm_regs[8 * 16];
    uint8_t dummy2[224];
};

static struct fpxstate fpx_state __attribute__((aligned(16)));
static struct fpxstate fpx_state2 __attribute__((aligned(16)));

void test_fxsave(void)
{
    struct fpxstate *fp = &fpx_state;
    struct fpxstate *fp2 = &fpx_state2;
    int i, nb_xmm;
    XMMReg a, b;
    a.q[0] = test_values[0][0];
    a.q[1] = test_values[0][1];
    b.q[0] = test_values[1][0];
    b.q[1] = test_values[1][1];

    asm("movdqa %2, %%xmm0\n"
        "movdqa %3, %%xmm7\n"
#if defined(__x86_64__)
        "movdqa %2, %%xmm15\n"
#endif
        " fld1\n"
        " fldpi\n"
        " fldln2\n"
        " fxsave %0\n"
        " fxrstor %0\n"
        " fxsave %1\n"
        " fninit\n"
        : "=m" (*(uint32_t *)fp2), "=m" (*(uint32_t *)fp) 
        : "m" (a), "m" (b));
    printf("fpuc=%04x\n", fp->fpuc);
    printf("fpus=%04x\n", fp->fpus);
    printf("fptag=%04x\n", fp->fptag);
    for(i = 0; i < 3; i++) {
        printf("ST%d: " FMT64X " %04x\n",
               i, 
               *(uint64_t *)&fp->fpregs1[i * 16],
               *(uint16_t *)&fp->fpregs1[i * 16 + 8]);
    }
    printf("mxcsr=%08x\n", fp->mxcsr & 0x1f80);
#if defined(__x86_64__)
    nb_xmm = 16;
#else
    nb_xmm = 8;
#endif
    for(i = 0; i < nb_xmm; i++) {
        printf("xmm%d: " FMT64X "" FMT64X "\n",
               i, 
               *(uint64_t *)&fp->xmm_regs[i * 16],
               *(uint64_t *)&fp->xmm_regs[i * 16 + 8]);
    }
}

void test_sse(void)
{
    XMMReg r, a, b;
    int i;

    MMX_OP2(punpcklbw);
    MMX_OP2(punpcklwd);
    MMX_OP2(punpckldq);
    MMX_OP2(packsswb);
    MMX_OP2(pcmpgtb);
    MMX_OP2(pcmpgtw);
    MMX_OP2(pcmpgtd);
    MMX_OP2(packuswb);
    MMX_OP2(punpckhbw);
    MMX_OP2(punpckhwd);
    MMX_OP2(punpckhdq);
    MMX_OP2(packssdw);
    MMX_OP2(pcmpeqb);
    MMX_OP2(pcmpeqw);
    MMX_OP2(pcmpeqd);

    MMX_OP2(paddq);
    MMX_OP2(pmullw);
    MMX_OP2(psubusb);
    MMX_OP2(psubusw);
    MMX_OP2(pminub);
    MMX_OP2(pand);
    MMX_OP2(paddusb);
    MMX_OP2(paddusw);
    MMX_OP2(pmaxub);
    MMX_OP2(pandn);

    MMX_OP2(pmulhuw);
    MMX_OP2(pmulhw);
    
    MMX_OP2(psubsb);
    MMX_OP2(psubsw);
    MMX_OP2(pminsw);
    MMX_OP2(por);
    MMX_OP2(paddsb);
    MMX_OP2(paddsw);
    MMX_OP2(pmaxsw);
    MMX_OP2(pxor);
    MMX_OP2(pmuludq);
    MMX_OP2(pmaddwd);
    MMX_OP2(psadbw);
    MMX_OP2(psubb);
    MMX_OP2(psubw);
    MMX_OP2(psubd);
    MMX_OP2(psubq);
    MMX_OP2(paddb);
    MMX_OP2(paddw);
    MMX_OP2(paddd);

    MMX_OP2(pavgb);
    MMX_OP2(pavgw);

    asm volatile ("pinsrw $1, %1, %0" : "=y" (r.q[0]) : "r" (0x12345678));
    printf("%-9s: r=" FMT64X "\n", "pinsrw", r.q[0]);

    asm volatile ("pinsrw $5, %1, %0" : "=x" (r.dq) : "r" (0x12345678));
    printf("%-9s: r=" FMT64X "" FMT64X "\n", "pinsrw", r.q[1], r.q[0]);

    a.q[0] = test_values[0][0];
    a.q[1] = test_values[0][1];
    asm volatile ("pextrw $1, %1, %0" : "=r" (r.l[0]) : "y" (a.q[0]));
    printf("%-9s: r=%08x\n", "pextrw", r.l[0]);

    asm volatile ("pextrw $5, %1, %0" : "=r" (r.l[0]) : "x" (a.dq));
    printf("%-9s: r=%08x\n", "pextrw", r.l[0]);

    asm volatile ("pmovmskb %1, %0" : "=r" (r.l[0]) : "y" (a.q[0]));
    printf("%-9s: r=%08x\n", "pmovmskb", r.l[0]);
    
    asm volatile ("pmovmskb %1, %0" : "=r" (r.l[0]) : "x" (a.dq));
    printf("%-9s: r=%08x\n", "pmovmskb", r.l[0]);

    {
        r.q[0] = -1;
        r.q[1] = -1;

        a.q[0] = test_values[0][0];
        a.q[1] = test_values[0][1];
        b.q[0] = test_values[1][0];
        b.q[1] = test_values[1][1];
        asm volatile("maskmovq %1, %0" : 
                     : "y" (a.q[0]), "y" (b.q[0]), "D" (&r)
                     : "memory"); 
        printf("%-9s: r=" FMT64X " a=" FMT64X " b=" FMT64X "\n", 
               "maskmov", 
               r.q[0], 
               a.q[0], 
               b.q[0]);
        asm volatile("maskmovdqu %1, %0" : 
                     : "x" (a.dq), "x" (b.dq), "D" (&r)
                     : "memory"); 
        printf("%-9s: r=" FMT64X "" FMT64X " a=" FMT64X "" FMT64X " b=" FMT64X "" FMT64X "\n", 
               "maskmov", 
               r.q[1], r.q[0], 
               a.q[1], a.q[0], 
               b.q[1], b.q[0]);
    }

    asm volatile ("emms");

    SSE_OP2(punpcklqdq);
    SSE_OP2(punpckhqdq);
    SSE_OP2(andps);
    SSE_OP2(andpd);
    SSE_OP2(andnps);
    SSE_OP2(andnpd);
    SSE_OP2(orps);
    SSE_OP2(orpd);
    SSE_OP2(xorps);
    SSE_OP2(xorpd);

    SSE_OP2(unpcklps);
    SSE_OP2(unpcklpd);
    SSE_OP2(unpckhps);
    SSE_OP2(unpckhpd);

    SHUF_OP(shufps, 0x78);
    SHUF_OP(shufpd, 0x02);

    PSHUF_OP(pshufd, 0x78);
    PSHUF_OP(pshuflw, 0x78);
    PSHUF_OP(pshufhw, 0x78);

    SHIFT_OP(psrlw, 7);
    SHIFT_OP(psrlw, 16);
    SHIFT_OP(psraw, 7);
    SHIFT_OP(psraw, 16);
    SHIFT_OP(psllw, 7);
    SHIFT_OP(psllw, 16);

    SHIFT_OP(psrld, 7);
    SHIFT_OP(psrld, 32);
    SHIFT_OP(psrad, 7);
    SHIFT_OP(psrad, 32);
    SHIFT_OP(pslld, 7);
    SHIFT_OP(pslld, 32);

    SHIFT_OP(psrlq, 7);
    SHIFT_OP(psrlq, 32);
    SHIFT_OP(psllq, 7);
    SHIFT_OP(psllq, 32);

    SHIFT_IM(psrldq, 16);
    SHIFT_IM(psrldq, 7);
    SHIFT_IM(pslldq, 16);
    SHIFT_IM(pslldq, 7);

    MOVMSK(movmskps);
    MOVMSK(movmskpd);

    /* FPU specific ops */

    {
        uint32_t mxcsr;
        asm volatile("stmxcsr %0" : "=m" (mxcsr));
        printf("mxcsr=%08x\n", mxcsr & 0x1f80);
        asm volatile("ldmxcsr %0" : : "m" (mxcsr));
    }

    test_sse_comi(2, -1);
    test_sse_comi(2, 2);
    test_sse_comi(2, 3);
    test_sse_comi(2, q_nan.d);
    test_sse_comi(q_nan.d, -1);

    for(i = 0; i < 2; i++) {
        a.s[0] = 2.7;
        a.s[1] = 3.4;
        a.s[2] = 4;
        a.s[3] = -6.3;
        b.s[0] = 45.7;
        b.s[1] = 353.4;
        b.s[2] = 4;
        b.s[3] = 56.3;
        if (i == 1) {
            a.s[0] = q_nan.d;
            b.s[3] = q_nan.d;
        }

        SSE_OPS(add);
        SSE_OPS(mul);
        SSE_OPS(su