📄 cpu.h
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#define SPR_58x_LCTRL2 (0x09D)#define SPR_58x_ICTRL (0x09E)#define SPR_58x_BAR (0x09F)#define SPR_VRSAVE (0x100)#define SPR_USPRG0 (0x100)#define SPR_USPRG4 (0x104)#define SPR_USPRG5 (0x105)#define SPR_USPRG6 (0x106)#define SPR_USPRG7 (0x107)#define SPR_VTBL (0x10C)#define SPR_VTBU (0x10D)#define SPR_SPRG0 (0x110)#define SPR_SPRG1 (0x111)#define SPR_SPRG2 (0x112)#define SPR_SPRG3 (0x113)#define SPR_SPRG4 (0x114)#define SPR_SCOMC (0x114)#define SPR_SPRG5 (0x115)#define SPR_SCOMD (0x115)#define SPR_SPRG6 (0x116)#define SPR_SPRG7 (0x117)#define SPR_ASR (0x118)#define SPR_EAR (0x11A)#define SPR_TBL (0x11C)#define SPR_TBU (0x11D)#define SPR_SVR (0x11E)#define SPR_440_PIR (0x11E)#define SPR_PVR (0x11F)#define SPR_HSPRG0 (0x130)#define SPR_440_DBSR (0x130)#define SPR_HSPRG1 (0x131)#define SPR_440_DBCR0 (0x134)#define SPR_IBCR (0x135)#define SPR_440_DBCR1 (0x135)#define SPR_DBCR (0x136)#define SPR_HDEC (0x136)#define SPR_440_DBCR2 (0x136)#define SPR_HIOR (0x137)#define SPR_MBAR (0x137)#define SPR_RMOR (0x138)#define SPR_440_IAC1 (0x138)#define SPR_HRMOR (0x139)#define SPR_440_IAC2 (0x139)#define SPR_HSSR0 (0x13A)#define SPR_440_IAC3 (0x13A)#define SPR_HSSR1 (0x13B)#define SPR_440_IAC4 (0x13B)#define SPR_LPCR (0x13C)#define SPR_440_DAC1 (0x13C)#define SPR_LPIDR (0x13D)#define SPR_DABR2 (0x13D)#define SPR_440_DAC2 (0x13D)#define SPR_440_DVC1 (0x13E)#define SPR_440_DVC2 (0x13F)#define SPR_440_TSR (0x150)#define SPR_440_TCR (0x154)#define SPR_440_IVOR0 (0x190)#define SPR_440_IVOR1 (0x191)#define SPR_440_IVOR2 (0x192)#define SPR_440_IVOR3 (0x193)#define SPR_440_IVOR4 (0x194)#define SPR_440_IVOR5 (0x195)#define SPR_440_IVOR6 (0x196)#define SPR_440_IVOR7 (0x197)#define SPR_440_IVOR8 (0x198)#define SPR_440_IVOR9 (0x199)#define SPR_440_IVOR10 (0x19A)#define SPR_440_IVOR11 (0x19B)#define SPR_440_IVOR12 (0x19C)#define SPR_440_IVOR13 (0x19D)#define SPR_440_IVOR14 (0x19E)#define SPR_440_IVOR15 (0x19F)#define SPR_IBAT0U (0x210)#define SPR_IBAT0L (0x211)#define SPR_IBAT1U (0x212)#define SPR_IBAT1L (0x213)#define SPR_IBAT2U (0x214)#define SPR_IBAT2L (0x215)#define SPR_IBAT3U (0x216)#define SPR_IBAT3L (0x217)#define SPR_DBAT0U (0x218)#define SPR_DBAT0L (0x219)#define SPR_DBAT1U (0x21A)#define SPR_DBAT1L (0x21B)#define SPR_DBAT2U (0x21C)#define SPR_DBAT2L (0x21D)#define SPR_DBAT3U (0x21E)#define SPR_DBAT3L (0x21F)#define SPR_IBAT4U (0x230)#define SPR_IBAT4L (0x231)#define SPR_IBAT5U (0x232)#define SPR_IBAT5L (0x233)#define SPR_IBAT6U (0x234)#define SPR_IBAT6L (0x235)#define SPR_IBAT7U (0x236)#define SPR_IBAT7L (0x237)#define SPR_DBAT4U (0x238)#define SPR_DBAT4L (0x239)#define SPR_DBAT5U (0x23A)#define SPR_DBAT5L (0x23B)#define SPR_DBAT6U (0x23C)#define SPR_DBAT6L (0x23D)#define SPR_DBAT7U (0x23E)#define SPR_DBAT7L (0x23F)#define SPR_440_INV0 (0x370)#define SPR_440_INV1 (0x371)#define SPR_440_INV2 (0x372)#define SPR_440_INV3 (0x373)#define SPR_440_IVT0 (0x374)#define SPR_440_IVT1 (0x375)#define SPR_440_IVT2 (0x376)#define SPR_440_IVT3 (0x377)#define SPR_440_DNV0 (0x390)#define SPR_440_DNV1 (0x391)#define SPR_440_DNV2 (0x392)#define SPR_440_DNV3 (0x393)#define SPR_440_DVT0 (0x394)#define SPR_440_DVT1 (0x395)#define SPR_440_DVT2 (0x396)#define SPR_440_DVT3 (0x397)#define SPR_440_DVLIM (0x398)#define SPR_440_IVLIM (0x399)#define SPR_440_RSTCFG (0x39B)#define SPR_440_DCBTRL (0x39C)#define SPR_440_DCBTRH (0x39D)#define SPR_440_ICBTRL (0x39E)#define SPR_440_ICBTRH (0x39F)#define SPR_UMMCR0 (0x3A8)#define SPR_UPMC1 (0x3A9)#define SPR_UPMC2 (0x3AA)#define SPR_USIA (0x3AB)#define SPR_UMMCR1 (0x3AC)#define SPR_UPMC3 (0x3AD)#define SPR_UPMC4 (0x3AE)#define SPR_USDA (0x3AF)#define SPR_40x_ZPR (0x3B0)#define SPR_40x_PID (0x3B1)#define SPR_440_MMUCR (0x3B2)#define SPR_4xx_CCR0 (0x3B3)#define SPR_405_IAC3 (0x3B4)#define SPR_405_IAC4 (0x3B5)#define SPR_405_DVC1 (0x3B6)#define SPR_405_DVC2 (0x3B7)#define SPR_MMCR0 (0x3B8)#define SPR_PMC1 (0x3B9)#define SPR_40x_SGR (0x3B9)#define SPR_PMC2 (0x3BA)#define SPR_40x_DCWR (0x3BA)#define SPR_SIA (0x3BB)#define SPR_405_SLER (0x3BB)#define SPR_MMCR1 (0x3BC)#define SPR_405_SU0R (0x3BC)#define SPR_PMC3 (0x3BD)#define SPR_405_DBCR1 (0x3BD)#define SPR_PMC4 (0x3BE)#define SPR_SDA (0x3BF)#define SPR_403_VTBL (0x3CC)#define SPR_403_VTBU (0x3CD)#define SPR_DMISS (0x3D0)#define SPR_DCMP (0x3D1)#define SPR_DHASH1 (0x3D2)#define SPR_DHASH2 (0x3D3)#define SPR_4xx_ICDBDR (0x3D3)#define SPR_IMISS (0x3D4)#define SPR_40x_ESR (0x3D4)#define SPR_ICMP (0x3D5)#define SPR_40x_DEAR (0x3D5)#define SPR_RPA (0x3D6)#define SPR_40x_EVPR (0x3D6)#define SPR_403_CDBCR (0x3D7)#define SPR_TCR (0x3D8)#define SPR_40x_TSR (0x3D8)#define SPR_IBR (0x3DA)#define SPR_40x_TCR (0x3DA)#define SPR_ESASR (0x3DB)#define SPR_40x_PIT (0x3DB)#define SPR_403_TBL (0x3DC)#define SPR_403_TBU (0x3DD)#define SPR_SEBR (0x3DE)#define SPR_40x_SRR2 (0x3DE)#define SPR_SER (0x3DF)#define SPR_40x_SRR3 (0x3DF)#define SPR_HID0 (0x3F0)#define SPR_40x_DBSR (0x3F0)#define SPR_HID1 (0x3F1)#define SPR_IABR (0x3F2)#define SPR_40x_DBCR0 (0x3F2)#define SPR_601_HID2 (0x3F2)#define SPR_HID2 (0x3F3)#define SPR_440_DBDR (0x3F3)#define SPR_40x_IAC1 (0x3F4)#define SPR_DABR (0x3F5)#define DABR_MASK (~(target_ulong)0x7)#define SPR_40x_IAC2 (0x3F5)#define SPR_601_HID5 (0x3F5)#define SPR_40x_DAC1 (0x3F6)#define SPR_40x_DAC2 (0x3F7)#define SPR_L2PM (0x3F8)#define SPR_750_HID2 (0x3F8)#define SPR_L2CR (0x3F9)#define SPR_IABR2 (0x3FA)#define SPR_40x_DCCR (0x3FA)#define SPR_ICTC (0x3FB)#define SPR_40x_ICCR (0x3FB)#define SPR_THRM1 (0x3FC)#define SPR_403_PBL1 (0x3FC)#define SPR_SP (0x3FD)#define SPR_THRM2 (0x3FD)#define SPR_403_PBU1 (0x3FD)#define SPR_LT (0x3FE)#define SPR_THRM3 (0x3FE)#define SPR_FPECR (0x3FE)#define SPR_403_PBL2 (0x3FE)#define SPR_PIR (0x3FF)#define SPR_403_PBU2 (0x3FF)#define SPR_601_HID15 (0x3FF)/* Memory access type : * may be needed for precise access rights control and precise exceptions. */enum { /* 1 bit to define user level / supervisor access */ ACCESS_USER = 0x00, ACCESS_SUPER = 0x01, /* Type of instruction that generated the access */ ACCESS_CODE = 0x10, /* Code fetch access */ ACCESS_INT = 0x20, /* Integer load/store access */ ACCESS_FLOAT = 0x30, /* floating point load/store access */ ACCESS_RES = 0x40, /* load/store with reservation */ ACCESS_EXT = 0x50, /* external access */ ACCESS_CACHE = 0x60, /* Cache manipulation */};/*****************************************************************************//* Exceptions */#define EXCP_NONE -1/* PowerPC hardware exceptions : exception vectors defined in PowerPC book 3 */#define EXCP_RESET 0x0100 /* System reset */#define EXCP_MACHINE_CHECK 0x0200 /* Machine check exception */#define EXCP_DSI 0x0300 /* Data storage exception */#define EXCP_DSEG 0x0380 /* Data segment exception */#define EXCP_ISI 0x0400 /* Instruction storage exception */#define EXCP_ISEG 0x0480 /* Instruction segment exception */#define EXCP_EXTERNAL 0x0500 /* External interruption */#define EXCP_ALIGN 0x0600 /* Alignment exception */#define EXCP_PROGRAM 0x0700 /* Program exception */#define EXCP_NO_FP 0x0800 /* Floating point unavailable exception */#define EXCP_DECR 0x0900 /* Decrementer exception */#define EXCP_HDECR 0x0980 /* Hypervisor decrementer exception */#define EXCP_SYSCALL 0x0C00 /* System call */#define EXCP_TRACE 0x0D00 /* Trace exception */#define EXCP_PERF 0x0F00 /* Performance monitor exception *//* Exceptions defined in PowerPC 32 bits programming environment manual */#define EXCP_FP_ASSIST 0x0E00 /* Floating-point assist *//* Implementation specific exceptions *//* 40x exceptions */#define EXCP_40x_PIT 0x1000 /* Programmable interval timer interrupt */#define EXCP_40x_FIT 0x1010 /* Fixed interval timer interrupt */#define EXCP_40x_WATCHDOG 0x1020 /* Watchdog timer exception */#define EXCP_40x_DTLBMISS 0x1100 /* Data TLB miss exception */#define EXCP_40x_ITLBMISS 0x1200 /* Instruction TLB miss exception */#define EXCP_40x_DEBUG 0x2000 /* Debug exception *//* 405 specific exceptions */#define EXCP_405_APU 0x0F20 /* APU unavailable exception *//* TLB assist exceptions (602/603) */#define EXCP_I_TLBMISS 0x1000 /* Instruction TLB miss */#define EXCP_DL_TLBMISS 0x1100 /* Data load TLB miss */#define EXCP_DS_TLBMISS 0x1200 /* Data store TLB miss *//* Breakpoint exceptions (602/603/604/620/740/745/750/755...) */#define EXCP_IABR 0x1300 /* Instruction address breakpoint */#define EXCP_SMI 0x1400 /* System management interrupt *//* Altivec related exceptions */#define EXCP_VPU 0x0F20 /* VPU unavailable exception *//* 601 specific exceptions */#define EXCP_601_IO 0x0600 /* IO error exception */#define EXCP_601_RUNM 0x2000 /* Run mode exception *//* 602 specific exceptions */#define EXCP_602_WATCHDOG 0x1500 /* Watchdog exception */#define EXCP_602_EMUL 0x1600 /* Emulation trap exception *//* G2 specific exceptions */#define EXCP_G2_CRIT 0x0A00 /* Critical interrupt *//* MPC740/745/750 & IBM 750 specific exceptions */#define EXCP_THRM 0x1700 /* Thermal management interrupt *//* 74xx specific exceptions */#define EXCP_74xx_VPUA 0x1600 /* VPU assist exception *//* 970FX specific exceptions */#define EXCP_970_SOFTP 0x1500 /* Soft patch exception */#define EXCP_970_MAINT 0x1600 /* Maintenance exception */#define EXCP_970_THRM 0x1800 /* Thermal exception */#define EXCP_970_VPUA 0x1700 /* VPU assist exception *//* End of exception vectors area */#define EXCP_PPC_MAX 0x4000/* Qemu exceptions: special cases we want to stop translation */#define EXCP_MTMSR 0x11000 /* mtmsr instruction: */ /* may change privilege level */#define EXCP_BRANCH 0x11001 /* branch instruction */#define EXCP_SYSCALL_USER 0x12000 /* System call in user mode only */#define EXCP_INTERRUPT_CRITICAL 0x13000 /* critical IRQ *//* Error codes */enum { /* Exception subtypes for EXCP_ALIGN */ EXCP_ALIGN_FP = 0x01, /* FP alignment exception */ EXCP_ALIGN_LST = 0x02, /* Unaligned mult/extern load/store */ EXCP_ALIGN_LE = 0x03, /* Multiple little-endian access */ EXCP_ALIGN_PROT = 0x04, /* Access cross protection boundary */ EXCP_ALIGN_BAT = 0x05, /* Access cross a BAT/seg boundary */ EXCP_ALIGN_CACHE = 0x06, /* Impossible dcbz access */ /* Exception subtypes for EXCP_PROGRAM */ /* FP exceptions */ EXCP_FP = 0x10, EXCP_FP_OX = 0x01, /* FP overflow */ EXCP_FP_UX = 0x02, /* FP underflow */ EXCP_FP_ZX = 0x03, /* FP divide by zero */ EXCP_FP_XX = 0x04, /* FP inexact */ EXCP_FP_VXNAN = 0x05, /* FP invalid SNaN op */ EXCP_FP_VXISI = 0x06, /* FP invalid infinite substraction */ EXCP_FP_VXIDI = 0x07, /* FP invalid infinite divide */ EXCP_FP_VXZDZ = 0x08, /* FP invalid zero divide */ EXCP_FP_VXIMZ = 0x09, /* FP invalid infinite * zero */ EXCP_FP_VXVC = 0x0A, /* FP invalid compare */ EXCP_FP_VXSOFT = 0x0B, /* FP invalid operation */ EXCP_FP_VXSQRT = 0x0C, /* FP invalid square root */ EXCP_FP_VXCVI = 0x0D, /* FP invalid integer conversion */ /* Invalid instruction */ EXCP_INVAL = 0x20, EXCP_INVAL_INVAL = 0x01, /* Invalid instruction */ EXCP_INVAL_LSWX = 0x02, /* Invalid lswx instruction */ EXCP_INVAL_SPR = 0x03, /* Invalid SPR access */ EXCP_INVAL_FP = 0x04, /* Unimplemented mandatory fp instr */ /* Privileged instruction */ EXCP_PRIV = 0x30, EXCP_PRIV_OPC = 0x01, EXCP_PRIV_REG = 0x02, /* Trap */ EXCP_TRAP = 0x40,};/*****************************************************************************/#endif /* !defined (__CPU_PPC_H__) */⌨️ 快捷键说明
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