cpu.h

qemu虚拟机代码

/*
 *  PowerPC emulation cpu definitions for qemu.
 * 
 *  Copyright (c) 2003-2005 Jocelyn Mayer
 *
 * This library is free software; you can redistribute it and/or
 * modify it under the terms of the GNU Lesser General Public
 * License as published by the Free Software Foundation; either
 * version 2 of the License, or (at your option) any later version.
 *
 * This library is distributed in the hope that it will be useful,
 * but WITHOUT ANY WARRANTY; without even the implied warranty of
 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
 * Lesser General Public License for more details.
 *
 * You should have received a copy of the GNU Lesser General Public
 * License along with this library; if not, write to the Free Software
 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
 */
#if !defined (__CPU_PPC_H__)
#define __CPU_PPC_H__

#include "config.h"

#define TARGET_LONG_BITS 32

#include "cpu-defs.h"

#include <setjmp.h>

#include "softfloat.h"

#define TARGET_HAS_ICE 1

/* XXX: this should be tunable: PowerPC 601 & 64 bits PowerPC
 *                              have different cache line sizes
 */
#define ICACHE_LINE_SIZE 32
#define DCACHE_LINE_SIZE 32

/* XXX: put this in a common place */
#define likely(x)   __builtin_expect(!!(x), 1)

/*****************************************************************************/
/* PVR definitions for most known PowerPC */
enum {
    /* PowerPC 401 cores */
    CPU_PPC_401A1     = 0x00210000,
    CPU_PPC_401B2     = 0x00220000,
    CPU_PPC_401C2     = 0x00230000,
    CPU_PPC_401D2     = 0x00240000,
    CPU_PPC_401E2     = 0x00250000,
    CPU_PPC_401F2     = 0x00260000,
    CPU_PPC_401G2     = 0x00270000,
    CPU_PPC_IOP480    = 0x40100000,
    /* PowerPC 403 cores */
    CPU_PPC_403GA     = 0x00200000,
    CPU_PPC_403GB     = 0x00200100,
    CPU_PPC_403GC     = 0x00200200,
    CPU_PPC_403GCX    = 0x00201400,
    /* PowerPC 405 cores */
    CPU_PPC_405       = 0x40110000,
    CPU_PPC_405EP     = 0x51210000,
    CPU_PPC_405GPR    = 0x50910000,
    CPU_PPC_405D2     = 0x20010000,
    CPU_PPC_405D4     = 0x41810000,
    CPU_PPC_NPE405H   = 0x41410000,
    CPU_PPC_NPE405L   = 0x41610000,
#if 0
    CPU_PPC_STB02     = xxx,
#endif
    CPU_PPC_STB03     = 0x40310000,
#if 0
    CPU_PPC_STB04     = xxx,
#endif
    CPU_PPC_STB25     = 0x51510000,
#if 0
    CPU_PPC_STB130    = xxx,
#endif
    /* PowerPC 440 cores */
    CPU_PPC_440EP     = 0x42220000,
    CPU_PPC_440GP     = 0x40120400,
    CPU_PPC_440GX     = 0x51B20000,
    /* PowerPC MPC 8xx cores */
    CPU_PPC_8540      = 0x80200000,
    CPU_PPC_8xx       = 0x00500000,
    CPU_PPC_8240      = 0x00810100,
    CPU_PPC_8245      = 0x00811014,
    /* PowerPC 6xx cores */
    CPU_PPC_601       = 0x00010000,
    CPU_PPC_602       = 0x00050000,
    CPU_PPC_603       = 0x00030000,
    CPU_PPC_603E      = 0x00060000,
    CPU_PPC_603EV     = 0x00070000,
    CPU_PPC_603R      = 0x00071000,
    CPU_PPC_G2        = 0x80810000,
    CPU_PPC_G2LE      = 0x80820000,
    CPU_PPC_604       = 0x00040000,
    CPU_PPC_604E      = 0x00090000,
    CPU_PPC_604R      = 0x000a0000,
    /* PowerPC 74x/75x cores (aka G3) */
    CPU_PPC_74x       = 0x00080000,
    CPU_PPC_755       = 0x00083000,
    CPU_PPC_74xP      = 0x10080000,
    CPU_PPC_750CXE22  = 0x00082202,
    CPU_PPC_750CXE24  = 0x00082214,
    CPU_PPC_750CXE24b = 0x00083214,
    CPU_PPC_750CXE31  = 0x00083211,
    CPU_PPC_750CXE31b = 0x00083311,
#define CPU_PPC_750CXE CPU_PPC_750CXE31b
    CPU_PPC_750FX     = 0x70000000,
    CPU_PPC_750GX     = 0x70020000,
    /* PowerPC 74xx cores (aka G4) */
    CPU_PPC_7400      = 0x000C0000,
    CPU_PPC_7410      = 0x800C0000,
    CPU_PPC_7441      = 0x80000200,
    CPU_PPC_7450      = 0x80000000,
    CPU_PPC_7451      = 0x80000203,
    CPU_PPC_7455      = 0x80010000,
    CPU_PPC_7457      = 0x80020000,
    CPU_PPC_7457A     = 0x80030000,
    /* 64 bits PowerPC */
    CPU_PPC_620       = 0x00140000,
    CPU_PPC_630       = 0x00400000,
    CPU_PPC_631       = 0x00410000,
    CPU_PPC_POWER4    = 0x00350000,
    CPU_PPC_POWER4P   = 0x00380000,
    CPU_PPC_POWER5    = 0x003A0000,
    CPU_PPC_POWER5P   = 0x003B0000,
    CPU_PPC_970       = 0x00390000,
    CPU_PPC_970FX     = 0x003C0000,
    CPU_PPC_RS64      = 0x00330000,
    CPU_PPC_RS64II    = 0x00340000,
    CPU_PPC_RS64III   = 0x00360000,
    CPU_PPC_RS64IV    = 0x00370000,
    /* Original POWER */
    /* XXX: should be POWER (RIOS), RSC3308, RSC4608,
     * POWER2 (RIOS2) & RSC2 (P2SC) here
     */
#if 0
    CPU_POWER         = xxx,
#endif
#if 0
    CPU_POWER2        = xxx,
#endif
};

/* System version register (used on MPC 8xx) */
enum {
    PPC_SVR_8540      = 0x80300000,
    PPC_SVR_8541E     = 0x807A0000,
    PPC_SVR_8555E     = 0x80790000,
    PPC_SVR_8560      = 0x80700000,
};

/*****************************************************************************/
/* Instruction types */
enum {
    PPC_NONE        = 0x00000000,
    /* integer operations instructions             */
    /* flow control instructions                   */
    /* virtual memory instructions                 */
    /* ld/st with reservation instructions         */
    /* cache control instructions                  */
    /* spr/msr access instructions                 */
    PPC_INSNS_BASE  = 0x00000001,
#define PPC_INTEGER PPC_INSNS_BASE
#define PPC_FLOW    PPC_INSNS_BASE
#define PPC_MEM     PPC_INSNS_BASE
#define PPC_RES     PPC_INSNS_BASE
#define PPC_CACHE   PPC_INSNS_BASE
#define PPC_MISC    PPC_INSNS_BASE
    /* floating point operations instructions      */
    PPC_FLOAT       = 0x00000002,
    /* more floating point operations instructions */
    PPC_FLOAT_EXT   = 0x00000004,
    /* external control instructions               */
    PPC_EXTERN      = 0x00000008,
    /* segment register access instructions        */
    PPC_SEGMENT     = 0x00000010,
    /* Optional cache control instructions         */
    PPC_CACHE_OPT   = 0x00000020,
    /* Optional floating point op instructions     */
    PPC_FLOAT_OPT   = 0x00000040,
    /* Optional memory control instructions        */
    PPC_MEM_TLBIA   = 0x00000080,
    PPC_MEM_TLBIE   = 0x00000100,
    PPC_MEM_TLBSYNC = 0x00000200,
    /* eieio & sync                                */
    PPC_MEM_SYNC    = 0x00000400,
    /* PowerPC 6xx TLB management instructions     */
    PPC_6xx_TLB     = 0x00000800,
    /* Altivec support                             */
    PPC_ALTIVEC     = 0x00001000,
    /* Time base support                           */
    PPC_TB          = 0x00002000,
    /* Embedded PowerPC dedicated instructions     */
    PPC_4xx_COMMON  = 0x00004000,
    /* PowerPC 40x exception model                 */
    PPC_40x_EXCP    = 0x00008000,
    /* PowerPC 40x specific instructions           */
    PPC_40x_SPEC    = 0x00010000,
    /* PowerPC 405 Mac instructions                */
    PPC_405_MAC     = 0x00020000,
    /* PowerPC 440 specific instructions           */
    PPC_440_SPEC    = 0x00040000,
    /* Specific extensions */
    /* Power-to-PowerPC bridge (601)               */
    PPC_POWER_BR    = 0x00080000,
    /* PowerPC 602 specific */
    PPC_602_SPEC    = 0x00100000,
    /* Deprecated instructions                     */
    /* Original POWER instruction set              */
    PPC_POWER       = 0x00200000,
    /* POWER2 instruction set extension            */
    PPC_POWER2      = 0x00400000,
    /* Power RTC support */
    PPC_POWER_RTC   = 0x00800000,
    /* 64 bits PowerPC instructions                */
    /* 64 bits PowerPC instruction set             */
    PPC_64B         = 0x01000000,
    /* 64 bits hypervisor extensions               */
    PPC_64H         = 0x02000000,
    /* 64 bits PowerPC "bridge" features           */
    PPC_64_BRIDGE   = 0x04000000,
};

/* CPU run-time flags (MMU and exception model) */
enum {
    /* MMU model */
#define PPC_FLAGS_MMU_MASK (0x0000000F)
    /* Standard 32 bits PowerPC MMU */
    PPC_FLAGS_MMU_32B      = 0x00000000,
    /* Standard 64 bits PowerPC MMU */
    PPC_FLAGS_MMU_64B      = 0x00000001,
    /* PowerPC 601 MMU */
    PPC_FLAGS_MMU_601      = 0x00000002,
    /* PowerPC 6xx MMU with software TLB */
    PPC_FLAGS_MMU_SOFT_6xx = 0x00000003,
    /* PowerPC 4xx MMU with software TLB */
    PPC_FLAGS_MMU_SOFT_4xx = 0x00000004,
    /* PowerPC 403 MMU */
    PPC_FLAGS_MMU_403      = 0x00000005,
    /* Exception model */
#define PPC_FLAGS_EXCP_MASK (0x000000F0)
    /* Standard PowerPC exception model */
    PPC_FLAGS_EXCP_STD     = 0x00000000,
    /* PowerPC 40x exception model */
    PPC_FLAGS_EXCP_40x     = 0x00000010,
    /* PowerPC 601 exception model */
    PPC_FLAGS_EXCP_601     = 0x00000020,
    /* PowerPC 602 exception model */
    PPC_FLAGS_EXCP_602     = 0x00000030,
    /* PowerPC 603 exception model */
    PPC_FLAGS_EXCP_603     = 0x00000040,
    /* PowerPC 604 exception model */
    PPC_FLAGS_EXCP_604     = 0x00000050,
    /* PowerPC 7x0 exception model */
    PPC_FLAGS_EXCP_7x0     = 0x00000060,
    /* PowerPC 7x5 exception model */
    PPC_FLAGS_EXCP_7x5     = 0x00000070,
    /* PowerPC 74xx exception model */
    PPC_FLAGS_EXCP_74xx    = 0x00000080,
    /* PowerPC 970 exception model */
    PPC_FLAGS_EXCP_970     = 0x00000090,
};

#define PPC_MMU(env) (env->flags & PPC_FLAGS_MMU_MASK)
#define PPC_EXCP(env) (env->flags & PPC_FLAGS_EXCP_MASK)

/*****************************************************************************/
/* Supported instruction set definitions */
/* This generates an empty opcode table... */
#define PPC_INSNS_TODO (PPC_NONE)
#define PPC_FLAGS_TODO (0x00000000)

/* PowerPC 40x instruction set */
#define PPC_INSNS_4xx (PPC_INSNS_BASE | PPC_MEM_TLBSYNC | PPC_4xx_COMMON)
/* PowerPC 401 */
#define PPC_INSNS_401 (PPC_INSNS_TODO)
#define PPC_FLAGS_401 (PPC_FLAGS_TODO)
/* PowerPC 403 */
#define PPC_INSNS_403 (PPC_INSNS_4xx | PPC_MEM_SYNC | PPC_MEM_TLBIA |         \
                       PPC_40x_EXCP | PPC_40x_SPEC)
#define PPC_FLAGS_403 (PPC_FLAGS_MMU_403 | PPC_FLAGS_EXCP_40x)
/* PowerPC 405 */
#define PPC_INSNS_405 (PPC_INSNS_4xx | PPC_MEM_SYNC | PPC_CACHE_OPT |         \
                       PPC_MEM_TLBIA | PPC_TB | PPC_40x_SPEC | PPC_40x_EXCP | \
                       PPC_405_MAC)
#define PPC_FLAGS_405 (PPC_FLAGS_MMU_SOFT_4xx | PPC_FLAGS_EXCP_40x)
/* PowerPC 440 */
#define PPC_INSNS_440 (PPC_INSNS_4xx | PPC_CACHE_OPT | PPC_405_MAC |          \
                       PPC_440_SPEC)
#define PPC_FLAGS_440 (PPC_FLAGS_TODO)
/* Non-embedded PowerPC */
#define PPC_INSNS_COMMON  (PPC_INSNS_BASE | PPC_FLOAT | PPC_MEM_SYNC |        \
                           PPC_SEGMENT | PPC_MEM_TLBIE)
/* PowerPC 601 */
#define PPC_INSNS_601 (PPC_INSNS_COMMON | PPC_EXTERN | PPC_POWER_BR)
#define PPC_FLAGS_601 (PPC_FLAGS_MMU_601 | PPC_FLAGS_EXCP_601)
/* PowerPC 602 */
#define PPC_INSNS_602 (PPC_INSNS_COMMON | PPC_FLOAT_EXT | PPC_6xx_TLB |       \
                       PPC_MEM_TLBSYNC | PPC_TB)
#define PPC_FLAGS_602 (PPC_FLAGS_MMU_SOFT_6xx | PPC_FLAGS_EXCP_602)
/* PowerPC 603 */
#define PPC_INSNS_603 (PPC_INSNS_COMMON | PPC_FLOAT_EXT | PPC_6xx_TLB |       \
                       PPC_MEM_TLBSYNC | PPC_EXTERN | PPC_TB)
#define PPC_FLAGS_603 (PPC_FLAGS_MMU_SOFT_6xx | PPC_FLAGS_EXCP_603)
/* PowerPC G2 */
#define PPC_INSNS_G2 (PPC_INSNS_COMMON | PPC_FLOAT_EXT | PPC_6xx_TLB |        \
                      PPC_MEM_TLBSYNC | PPC_EXTERN | PPC_TB)
#define PPC_FLAGS_G2 (PPC_FLAGS_MMU_SOFT_6xx | PPC_FLAGS_EXCP_603)
/* PowerPC 604 */
#define PPC_INSNS_604 (PPC_INSNS_COMMON | PPC_FLOAT_EXT | PPC_EXTERN |        \
                       PPC_MEM_TLBSYNC | PPC_TB)
#define PPC_FLAGS_604 (PPC_FLAGS_MMU_32B | PPC_FLAGS_EXCP_604)
/* PowerPC 740/750 (aka G3) */
#define PPC_INSNS_7x0 (PPC_INSNS_COMMON | PPC_FLOAT_EXT | PPC_EXTERN |        \
                       PPC_MEM_TLBSYNC | PPC_TB)
#define PPC_FLAGS_7x0 (PPC_FLAGS_MMU_32B | PPC_FLAGS_EXCP_7x0)
/* PowerPC 745/755 */
#define PPC_INSNS_7x5 (PPC_INSNS_COMMON | PPC_FLOAT_EXT | PPC_EXTERN |        \
                       PPC_MEM_TLBSYNC | PPC_TB | PPC_6xx_TLB)
#define PPC_FLAGS_7x5 (PPC_FLAGS_MMU_SOFT_6xx | PPC_FLAGS_EXCP_7x5)
/* PowerPC 74xx (aka G4) */
#define PPC_INSNS_74xx (PPC_INSNS_COMMON | PPC_FLOAT_EXT | PPC_ALTIVEC |      \
                        PPC_MEM_TLBSYNC | PPC_TB)
#define PPC_FLAGS_74xx (PPC_FLAGS_MMU_32B | PPC_FLAGS_EXCP_74xx)

/* Default PowerPC will be 604/970 */
#define PPC_INSNS_PPC32 PPC_INSNS_604
#define PPC_FLAGS_PPC32 PPC_FLAGS_604
#if 0
#define PPC_INSNS_PPC64 PPC_INSNS_970
#define PPC_FLAGS_PPC64 PPC_FLAGS_970
#endif
#define PPC_INSNS_DEFAULT PPC_INSNS_604
#define PPC_FLAGS_DEFAULT PPC_FLAGS_604
typedef struct ppc_def_t ppc_def_t;

/*****************************************************************************/
/* Types used to describe some PowerPC registers */