📄 rtl8139.c
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/* writing 1 to interrupt status register bit clears it */ s->IntrStatus = 0; rtl8139_update_irq(s); s->IntrStatus = newStatus; rtl8139_update_irq(s);#endif}static uint32_t rtl8139_IntrStatus_read(RTL8139State *s){ uint32_t ret = s->IntrStatus;#ifdef DEBUG_RTL8139 printf("RTL8139: IntrStatus read(w) val=0x%04x\n", ret);#endif#if 0 /* reading ISR clears all interrupts */ s->IntrStatus = 0; rtl8139_update_irq(s);#endif return ret;}static void rtl8139_MultiIntr_write(RTL8139State *s, uint32_t val){#ifdef DEBUG_RTL8139 printf("RTL8139: MultiIntr write(w) val=0x%04x\n", val);#endif /* mask unwriteable bits */ val = SET_MASKED(val, 0xf000, s->MultiIntr); s->MultiIntr = val;}static uint32_t rtl8139_MultiIntr_read(RTL8139State *s){ uint32_t ret = s->MultiIntr;#ifdef DEBUG_RTL8139 printf("RTL8139: MultiIntr read(w) val=0x%04x\n", ret);#endif return ret;}static void rtl8139_io_writeb(void *opaque, uint8_t addr, uint32_t val){ RTL8139State *s = opaque; addr &= 0xff; switch (addr) { case MAC0 ... MAC0+5: s->phys[addr - MAC0] = val; break; case MAC0+6 ... MAC0+7: /* reserved */ break; case MAR0 ... MAR0+7: s->mult[addr - MAR0] = val; break; case ChipCmd: rtl8139_ChipCmd_write(s, val); break; case Cfg9346: rtl8139_Cfg9346_write(s, val); break; case TxConfig: /* windows driver sometimes writes using byte-lenth call */ rtl8139_TxConfig_writeb(s, val); break; case Config0: rtl8139_Config0_write(s, val); break; case Config1: rtl8139_Config1_write(s, val); break; case Config3: rtl8139_Config3_write(s, val); break; case Config4: rtl8139_Config4_write(s, val); break; case Config5: rtl8139_Config5_write(s, val); break; case MediaStatus: /* ignore */#ifdef DEBUG_RTL8139 printf("RTL8139: not implemented write(b) to MediaStatus val=0x%02x\n", val);#endif break; case HltClk:#ifdef DEBUG_RTL8139 printf("RTL8139: HltClk write val=0x%08x\n", val);#endif if (val == 'R') { s->clock_enabled = 1; } else if (val == 'H') { s->clock_enabled = 0; } break; case TxThresh:#ifdef DEBUG_RTL8139 printf("RTL8139C+ TxThresh write(b) val=0x%02x\n", val);#endif s->TxThresh = val; break; case TxPoll:#ifdef DEBUG_RTL8139 printf("RTL8139C+ TxPoll write(b) val=0x%02x\n", val);#endif if (val & (1 << 7)) {#ifdef DEBUG_RTL8139 printf("RTL8139C+ TxPoll high priority transmission (not implemented)\n");#endif //rtl8139_cplus_transmit(s); } if (val & (1 << 6)) {#ifdef DEBUG_RTL8139 printf("RTL8139C+ TxPoll normal priority transmission\n");#endif rtl8139_cplus_transmit(s); } break; default:#ifdef DEBUG_RTL8139 printf("RTL8139: not implemented write(b) addr=0x%x val=0x%02x\n", addr, val);#endif break; }}static void rtl8139_io_writew(void *opaque, uint8_t addr, uint32_t val){ RTL8139State *s = opaque; addr &= 0xfe; switch (addr) { case IntrMask: rtl8139_IntrMask_write(s, val); break; case IntrStatus: rtl8139_IntrStatus_write(s, val); break; case MultiIntr: rtl8139_MultiIntr_write(s, val); break; case RxBufPtr: rtl8139_RxBufPtr_write(s, val); break; case BasicModeCtrl: rtl8139_BasicModeCtrl_write(s, val); break; case BasicModeStatus: rtl8139_BasicModeStatus_write(s, val); break; case NWayAdvert:#ifdef DEBUG_RTL8139 printf("RTL8139: NWayAdvert write(w) val=0x%04x\n", val);#endif s->NWayAdvert = val; break; case NWayLPAR:#ifdef DEBUG_RTL8139 printf("RTL8139: forbidden NWayLPAR write(w) val=0x%04x\n", val);#endif break; case NWayExpansion:#ifdef DEBUG_RTL8139 printf("RTL8139: NWayExpansion write(w) val=0x%04x\n", val);#endif s->NWayExpansion = val; break; case CpCmd: rtl8139_CpCmd_write(s, val); break; default:#ifdef DEBUG_RTL8139 printf("RTL8139: ioport write(w) addr=0x%x val=0x%04x via write(b)\n", addr, val);#endif#ifdef TARGET_WORDS_BIGENDIAN rtl8139_io_writeb(opaque, addr, (val >> 8) & 0xff); rtl8139_io_writeb(opaque, addr + 1, val & 0xff);#else rtl8139_io_writeb(opaque, addr, val & 0xff); rtl8139_io_writeb(opaque, addr + 1, (val >> 8) & 0xff);#endif break; }}static void rtl8139_io_writel(void *opaque, uint8_t addr, uint32_t val){ RTL8139State *s = opaque; addr &= 0xfc; switch (addr) { case RxMissed:#ifdef DEBUG_RTL8139 printf("RTL8139: RxMissed clearing on write\n");#endif s->RxMissed = 0; break; case TxConfig: rtl8139_TxConfig_write(s, val); break; case RxConfig: rtl8139_RxConfig_write(s, val); break; case TxStatus0 ... TxStatus0+4*4-1: rtl8139_TxStatus_write(s, addr-TxStatus0, val); break; case TxAddr0 ... TxAddr0+4*4-1: rtl8139_TxAddr_write(s, addr-TxAddr0, val); break; case RxBuf: rtl8139_RxBuf_write(s, val); break; case RxRingAddrLO:#ifdef DEBUG_RTL8139 printf("RTL8139: C+ RxRing low bits write val=0x%08x\n", val);#endif s->RxRingAddrLO = val; break; case RxRingAddrHI:#ifdef DEBUG_RTL8139 printf("RTL8139: C+ RxRing high bits write val=0x%08x\n", val);#endif s->RxRingAddrHI = val; break; default:#ifdef DEBUG_RTL8139 printf("RTL8139: ioport write(l) addr=0x%x val=0x%08x via write(b)\n", addr, val);#endif#ifdef TARGET_WORDS_BIGENDIAN rtl8139_io_writeb(opaque, addr, (val >> 24) & 0xff); rtl8139_io_writeb(opaque, addr + 1, (val >> 16) & 0xff); rtl8139_io_writeb(opaque, addr + 2, (val >> 8) & 0xff); rtl8139_io_writeb(opaque, addr + 3, val & 0xff);#else rtl8139_io_writeb(opaque, addr, val & 0xff); rtl8139_io_writeb(opaque, addr + 1, (val >> 8) & 0xff); rtl8139_io_writeb(opaque, addr + 2, (val >> 16) & 0xff); rtl8139_io_writeb(opaque, addr + 3, (val >> 24) & 0xff);#endif break; }}static uint32_t rtl8139_io_readb(void *opaque, uint8_t addr){ RTL8139State *s = opaque; int ret; addr &= 0xff; switch (addr) { case MAC0 ... MAC0+5: ret = s->phys[addr - MAC0]; break; case MAC0+6 ... MAC0+7: ret = 0; break; case MAR0 ... MAR0+7: ret = s->mult[addr - MAR0]; break; case ChipCmd: ret = rtl8139_ChipCmd_read(s); break; case Cfg9346: ret = rtl8139_Cfg9346_read(s); break; case Config0: ret = rtl8139_Config0_read(s); break; case Config1: ret = rtl8139_Config1_read(s); break; case Config3: ret = rtl8139_Config3_read(s); break; case Config4: ret = rtl8139_Config4_read(s); break; case Config5: ret = rtl8139_Config5_read(s); break; case MediaStatus: ret = 0xd0;#ifdef DEBUG_RTL8139 printf("RTL8139: MediaStatus read 0x%x\n", ret);#endif break; case HltClk: ret = s->clock_enabled;#ifdef DEBUG_RTL8139 printf("RTL8139: HltClk read 0x%x\n", ret);#endif break; case PCIRevisionID: ret = 0x10;#ifdef DEBUG_RTL8139 printf("RTL8139: PCI Revision ID read 0x%x\n", ret);#endif break; case TxThresh: ret = s->TxThresh;#ifdef DEBUG_RTL8139 printf("RTL8139C+ TxThresh read(b) val=0x%02x\n", ret);#endif break; case 0x43: /* Part of TxConfig register. Windows driver tries to read it */ ret = s->TxConfig >> 24;#ifdef DEBUG_RTL8139 printf("RTL8139C TxConfig at 0x43 read(b) val=0x%02x\n", ret);#endif break; default:#ifdef DEBUG_RTL8139 printf("RTL8139: not implemented read(b) addr=0x%x\n", addr);#endif ret = 0; break; } return ret;}static uint32_t rtl8139_io_readw(void *opaque, uint8_t addr){ RTL8139State *s = opaque; uint32_t ret; addr &= 0xfe; /* mask lower bit */ switch (addr) { case IntrMask: ret = rtl8139_IntrMask_read(s); break; case IntrStatus: ret = rtl8139_IntrStatus_read(s); break; case MultiIntr: ret = rtl8139_MultiIntr_read(s); break; case RxBufPtr: ret = rtl8139_RxBufPtr_read(s); break; case BasicModeCtrl: ret = rtl8139_BasicModeCtrl_read(s); break; case BasicModeStatus: ret = rtl8139_BasicModeStatus_read(s); break; case NWayAdvert: ret = s->NWayAdvert;#ifdef DEBUG_RTL8139 printf("RTL8139: NWayAdvert read(w) val=0x%04x\n", ret);#endif break; case NWayLPAR: ret = s->NWayLPAR;#ifdef DEBUG_RTL8139 printf("RTL8139: NWayLPAR read(w) val=0x%04x\n", ret);#endif break; case NWayExpansion: ret = s->NWayExpansion;#ifdef DEBUG_RTL8139 printf("RTL8139: NWayExpansion read(w) val=0x%04x\n", ret);#endif break; case CpCmd: ret = rtl8139_CpCmd_read(s); break; case TxSummary: ret = rtl8139_TSAD_read(s); break; case CSCR: ret = rtl8139_CSCR_read(s); break; default:#ifdef DEBUG_RTL8139 printf("RTL8139: ioport read(w) addr=0x%x via read(b)\n", addr);#endif#ifdef TARGET_WORDS_BIGENDIAN ret = rtl8139_io_readb(opaque, addr) << 8; ret |= rtl8139_io_readb(opaque, addr + 1);#else ret = rtl8139_io_readb(opaque, addr); ret |= rtl8139_io_readb(opaque, addr + 1) << 8;#endif#ifdef DEBUG_RTL8139 printf("RTL8139: ioport read(w) addr=0x%x val=0x%04x\n", addr, ret);#endif break; } return ret;}static uint32_t rtl8139_io_readl(void *opaque, uint8_t addr){ RTL8139State *s = opaque; uint32_t ret; addr &= 0xfc; /* also mask low 2 bits */ switch (addr) { case RxMissed: ret = s->RxMissed;#ifdef DEBUG_RTL8139 printf("RTL8139: RxMissed read val=0x%08x\n", ret);#endif break; case TxConfig: ret = rtl8139_TxConfig_read(s); break; case RxConfig: ret = rtl8139_RxConfig_read(s); break; case TxStatus0 ... TxStatus0+4*4-1: ret = rtl8139_TxStatus_read(s, addr-TxStatus0); break; case TxAddr0 ... TxAddr0+4*4-1: ret = rtl8139_TxAddr_read(s, addr-TxAddr0); break; case RxBuf: ret = rtl8139_RxBuf_read(s); break; case RxRingAddrLO: ret = s->RxRingAddrLO;#ifdef DEBUG_RTL8139 printf("RTL8139: C+ RxRing low bits read val=0x%08x\n", ret);#endif break; case RxRingAddrHI: ret = s->RxRingAddrHI;#ifdef DEBUG_RTL8139 printf("RTL8139: C+ RxRing high bits read
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