sh7750.c

qemu虚拟机代码

/*
 * SH7750 device
 * 
 * Copyright (c) 2005 Samuel Tardieu
 * 
 * Permission is hereby granted, free of charge, to any person obtaining a copy
 * of this software and associated documentation files (the "Software"), to deal
 * in the Software without restriction, including without limitation the rights
 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
 * copies of the Software, and to permit persons to whom the Software is
 * furnished to do so, subject to the following conditions:
 *
 * The above copyright notice and this permission notice shall be included in
 * all copies or substantial portions of the Software.
 *
 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
 * THE SOFTWARE.
 */
#include <stdio.h>
#include <assert.h>
#include "vl.h"
#include "sh7750_regs.h"
#include "sh7750_regnames.h"

typedef struct {
    uint8_t data[16];
    uint8_t length;		/* Number of characters in the FIFO */
    uint8_t write_idx;		/* Index of first character to write */
    uint8_t read_idx;		/* Index of first character to read */
} fifo;

#define NB_DEVICES 4

typedef struct SH7750State {
    /* CPU */
    CPUSH4State *cpu;
    /* Peripheral frequency in Hz */
    uint32_t periph_freq;
    /* SDRAM controller */
    uint16_t rfcr;
    /* First serial port */
    CharDriverState *serial1;
    uint8_t scscr1;
    uint8_t scsmr1;
    uint8_t scbrr1;
    uint8_t scssr1;
    uint8_t scssr1_read;
    uint8_t sctsr1;
    uint8_t sctsr1_loaded;
    uint8_t sctdr1;
    uint8_t scrdr1;
    /* Second serial port */
    CharDriverState *serial2;
    uint16_t sclsr2;
    uint16_t scscr2;
    uint16_t scfcr2;
    uint16_t scfsr2;
    uint16_t scsmr2;
    uint8_t scbrr2;
    fifo serial2_receive_fifo;
    fifo serial2_transmit_fifo;
    /* Timers */
    uint8_t tstr;
    /* Timer 0 */
    QEMUTimer *timer0;
    uint16_t tcr0;
    uint32_t tcor0;
    uint32_t tcnt0;
    /* IO ports */
    uint16_t gpioic;
    uint32_t pctra;
    uint32_t pctrb;
    uint16_t portdira;		/* Cached */
    uint16_t portpullupa;	/* Cached */
    uint16_t portdirb;		/* Cached */
    uint16_t portpullupb;	/* Cached */
    uint16_t pdtra;
    uint16_t pdtrb;
    uint16_t periph_pdtra;	/* Imposed by the peripherals */
    uint16_t periph_portdira;	/* Direction seen from the peripherals */
    uint16_t periph_pdtrb;	/* Imposed by the peripherals */
    uint16_t periph_portdirb;	/* Direction seen from the peripherals */
    sh7750_io_device *devices[NB_DEVICES];	/* External peripherals */
    /* Cache */
    uint32_t ccr;
} SH7750State;

/**********************************************************************
 Timers
**********************************************************************/

/* XXXXX At this time, timer0 works in underflow only mode, that is
   the value of tcnt0 is read at alarm computation time and cannot
   be read back by the guest OS */

static void start_timer0(SH7750State * s)
{
    uint64_t now, next, prescaler;

    if ((s->tcr0 & 6) == 6) {
	fprintf(stderr, "rtc clock for timer 0 not supported\n");
	assert(0);
    }

    if ((s->tcr0 & 7) == 5) {
	fprintf(stderr, "timer 0 configuration not supported\n");
	assert(0);
    }

    if ((s->tcr0 & 4) == 4)
	prescaler = 1024;
    else
	prescaler = 4 << (s->tcr0 & 3);

    now = qemu_get_clock(vm_clock);
    /* XXXXX */
    next =
	now + muldiv64(prescaler * s->tcnt0, ticks_per_sec,
		       s->periph_freq);
    if (next == now)
	next = now + 1;
    fprintf(stderr, "now=%016llx, next=%016llx\n", now, next);
    fprintf(stderr, "timer will underflow in %f seconds\n",
	    (float) (next - now) / (float) ticks_per_sec);

    qemu_mod_timer(s->timer0, next);
}

static void timer_start_changed(SH7750State * s)
{
    if (s->tstr & SH7750_TSTR_STR0) {
	start_timer0(s);
    } else {
	fprintf(stderr, "timer 0 is stopped\n");
	qemu_del_timer(s->timer0);
    }
}

static void timer0_cb(void *opaque)
{
    SH7750State *s = opaque;

    s->tcnt0 = (uint32_t) 0;	/* XXXXX */
    if (--s->tcnt0 == (uint32_t) - 1) {
	fprintf(stderr, "timer 0 underflow\n");
	s->tcnt0 = s->tcor0;
	s->tcr0 |= SH7750_TCR_UNF;
	if (s->tcr0 & SH7750_TCR_UNIE) {
	    fprintf(stderr,
		    "interrupt generation for timer 0 not supported\n");
	    assert(0);
	}
    }
    start_timer0(s);
}

static void init_timers(SH7750State * s)
{
    s->tcor0 = 0xffffffff;
    s->tcnt0 = 0xffffffff;
    s->timer0 = qemu_new_timer(vm_clock, &timer0_cb, s);
}

/**********************************************************************
 First serial port
**********************************************************************/

static int serial1_can_receive(void *opaque)
{
    SH7750State *s = opaque;

    return s->scscr1 & SH7750_SCSCR_RE;
}

static void serial1_receive_char(SH7750State * s, uint8_t c)
{
    if (s->scssr1 & SH7750_SCSSR1_RDRF) {
	s->scssr1 |= SH7750_SCSSR1_ORER;
	return;
    }

    s->scrdr1 = c;
    s->scssr1 |= SH7750_SCSSR1_RDRF;
}

static void serial1_receive(void *opaque, const uint8_t * buf, int size)
{
    SH7750State *s = opaque;
    int i;

    for (i = 0; i < size; i++) {
	serial1_receive_char(s, buf[i]);
    }
}

static void serial1_event(void *opaque, int event)
{
    assert(0);
}

static void serial1_maybe_send(SH7750State * s)
{
    uint8_t c;

    if (s->scssr1 & SH7750_SCSSR1_TDRE)
	return;
    c = s->sctdr1;
    s->scssr1 |= SH7750_SCSSR1_TDRE | SH7750_SCSSR1_TEND;
    if (s->scscr1 & SH7750_SCSCR_TIE) {
	fprintf(stderr, "interrupts for serial port 1 not implemented\n");
	assert(0);
    }
    /* XXXXX Check for errors in write */
    qemu_chr_write(s->serial1, &c, 1);
}

static void serial1_change_scssr1(SH7750State * s, uint8_t mem_value)
{
    uint8_t new_flags;

    /* If transmit disable, TDRE and TEND stays up */
    if ((s->scscr1 & SH7750_SCSCR_TE) == 0) {
	mem_value |= SH7750_SCSSR1_TDRE | SH7750_SCSSR1_TEND;
    }

    /* Only clear bits which have been read before and do not set any bit
       in the flags */
    new_flags = s->scssr1 & ~s->scssr1_read;	/* Preserve unread flags */
    new_flags &= mem_value | ~s->scssr1_read;	/* Clear read flags */

    s->scssr1 = (new_flags & 0xf8) | (mem_value & 1);
    s->scssr1_read &= mem_value;

    /* If TDRE has been cleared, TEND will also be cleared */
    if ((s->scssr1 & SH7750_SCSSR1_TDRE) == 0) {
	s->scssr1 &= ~SH7750_SCSSR1_TEND;
    }

    /* Check for transmission to start */
    serial1_maybe_send(s);
}

static void serial1_update_parameters(SH7750State * s)
{
    QEMUSerialSetParams ssp;

    if (s->scsmr1 & SH7750_SCSMR_CHR_7)
	ssp.data_bits = 7;
    else
	ssp.data_bits = 8;
    if (s->scsmr1 & SH7750_SCSMR_PE) {
	if (s->scsmr1 & SH7750_SCSMR_PM_ODD)
	    ssp.parity = 'O';
	else
	    ssp.parity = 'E';
    } else
	ssp.parity = 'N';
    if (s->scsmr1 & SH7750_SCSMR_STOP_2)
	ssp.stop_bits = 2;
    else
	ssp.stop_bits = 1;
    fprintf(stderr, "SCSMR1=%04x SCBRR1=%02x\n", s->scsmr1, s->scbrr1);
    ssp.speed = s->periph_freq /
	(32 * s->scbrr1 * (1 << (2 * (s->scsmr1 & 3)))) - 1;
    fprintf(stderr, "data bits=%d, stop bits=%d, parity=%c, speed=%d\n",
	    ssp.data_bits, ssp.stop_bits, ssp.parity, ssp.speed);
    qemu_chr_ioctl(s->serial1, CHR_IOCTL_SERIAL_SET_PARAMS, &ssp);
}

static void scscr1_changed(SH7750State * s)
{
    if (s->scscr1 & (SH7750_SCSCR_TE | SH7750_SCSCR_RE)) {
	if (!s->serial1) {
	    fprintf(stderr, "serial port 1 not bound to anything\n");
	    assert(0);
	}
	serial1_update_parameters(s);
    }
    if ((s->scscr1 & SH7750_SCSCR_RE) == 0) {
	s->scssr1 |= SH7750_SCSSR1_TDRE;
    }
}

static void init_serial1(SH7750State * s, int serial_nb)
{
    CharDriverState *chr;

    s->scssr1 = 0x84;
    chr = serial_hds[serial_nb];
    if (!chr) {
	fprintf(stderr,
		"no serial port associated to SH7750 first serial port\n");
	return;
    }

    s->serial1 = chr;
    qemu_chr_add_read_handler(chr, serial1_can_receive,
			      serial1_receive, s);
    qemu_chr_add_event_handler(chr, serial1_event);
}

/**********************************************************************
 Second serial port
**********************************************************************/

static int serial2_can_receive(void *opaque)
{
    SH7750State *s = opaque;
    static uint8_t max_fifo_size[] = { 15, 1, 4, 6, 8, 10, 12, 14 };

    return s->serial2_receive_fifo.length <
	max_fifo_size[(s->scfcr2 >> 9) & 7];
}

static void serial2_adjust_receive_flags(SH7750State * s)
{
    static uint8_t max_fifo_size[] = { 1, 4, 8, 14 };

    /* XXXXX Add interrupt generation */
    if (s->serial2_receive_fifo.length >=
	max_fifo_size[(s->scfcr2 >> 7) & 3]) {
	s->scfsr2 |= SH7750_SCFSR2_RDF;
	s->scfsr2 &= ~SH7750_SCFSR2_DR;
    } else {
	s->scfsr2 &= ~SH7750_SCFSR2_RDF;
	if (s->serial2_receive_fifo.length > 0)
	    s->scfsr2 |= SH7750_SCFSR2_DR;
	else
	    s->scfsr2 &= ~SH7750_SCFSR2_DR;
    }
}

static void serial2_append_char(SH7750State * s, uint8_t c)
{
    if (s->serial2_receive_fifo.length == 16) {
	/* Overflow */
	s->sclsr2 |= SH7750_SCLSR2_ORER;
	return;
    }

    s->serial2_receive_fifo.data[s->serial2_receive_fifo.write_idx++] = c;
    s->serial2_receive_fifo.length++;
    serial2_adjust_receive_flags(s);
}

static void serial2_receive(void *opaque, const uint8_t * buf, int size)
{
    SH7750State *s = opaque;
    int i;

    for (i = 0; i < size; i++)
	serial2_append_char(s, buf[i]);
}

static void serial2_event(void *opaque, int event)
{
    /* XXXXX */
    assert(0);
}

static void serial2_update_parameters(SH7750State * s)
{
    QEMUSerialSetParams ssp;

    if (s->scsmr2 & SH7750_SCSMR_CHR_7)
	ssp.data_bits = 7;
    else
	ssp.data_bits = 8;
    if (s->scsmr2 & SH7750_SCSMR_PE) {
	if (s->scsmr2 & SH7750_SCSMR_PM_ODD)
	    ssp.parity = 'O';
	else
	    ssp.parity = 'E';
    } else
	ssp.parity = 'N';
    if (s->scsmr2 & SH7750_SCSMR_STOP_2)
	ssp.stop_bits = 2;
    else
	ssp.stop_bits = 1;
    fprintf(stderr, "SCSMR2=%04x SCBRR2=%02x\n", s->scsmr2, s->scbrr2);
    ssp.speed = s->periph_freq /
	(32 * s->scbrr2 * (1 << (2 * (s->scsmr2 & 3)))) - 1;
    fprintf(stderr, "data bits=%d, stop bits=%d, parity=%c, speed=%d\n",
	    ssp.data_bits, ssp.stop_bits, ssp.parity, ssp.speed);
    qemu_chr_ioctl(s->serial2, CHR_IOCTL_SERIAL_SET_PARAMS, &ssp);
}

static void scscr2_changed(SH7750State * s)
{
    if (s->scscr2 & (SH7750_SCSCR_TE | SH7750_SCSCR_RE)) {
	if (!s->serial2) {
	    fprintf(stderr, "serial port 2 not bound to anything\n");
	    assert(0);
	}
	serial2_update_parameters(s);
    }
}

static void init_serial2(SH7750State * s, int serial_nb)
{
    CharDriverState *chr;

    s->scfsr2 = 0x0060;

    chr = serial_hds[serial_nb];
    if (!chr) {
	fprintf(stderr,
		"no serial port associated to SH7750 second serial port\n");
	return;
    }

    s->serial2 = chr;
    qemu_chr_add_read_handler(chr, serial2_can_receive,
			      serial2_receive, s);